__IO uint8_t IP[240];/*Offset:0x300(R/W)Interrupt Priority Register(8Bit wide)*/ //中断优先级寄存器阵列(8位)：中断0-239的中断优先级； //地址为：0xE000-E400——0xE000-E4EF；复位值：0
uint32_t RESERVED5[644]; //未定义的寄存器
__IO uint32_t STIR; /* Offset: 0xE00 (R/W)Software Trigger Interrupt Register*/ //STIR：软件触发中断寄存器（如写入8则触发中断8的中断）； //地址为：0xE000-EF00；复位值：- } NVIC_Type;
#define SCS_BASE (0xE000E000) /*System Control Space Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100) /*NVIC Base Address */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*NVIC configuration struct*/
typedef struct {
__I uint32_t CPUID; /*Offset: 0x000 (R/ ) CPUID Base Register*/ //CPUID: --;地址为：0xE000-ED00；复位值：0x410fc230
__IO uint32_t ICSR; /*Offset: 0x004(R/W)Interrupt Control and State Register*/ //ICSR:中断控制及状态寄存器；地址为：0xE000-ED04；复位值：0
__IO uint32_t VTOR; /*Offset: 0x008 (R/W) Vector Table Offset Register*/ //VTOR:向量表偏移寄存器；地址为：0xE000-ED08；复位值：-
__IO uint32_t AIRCR; /*Offset:0x00C(R/W)Application Interrupt and Reset Control Register*/
__IO uint32_t SCR; /*Offset: 0x010 (R/W) System Control Register*/
__IO uint32_t CCR; /*Offset: 0x014 (R/W) Configuration Control Register*/
__IO uint8_t SHP[12]; /*Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IO uint32_t SHCSR; /*Offset: 0x024 (R/W) System Handler Control and State Register*/
__IO uint32_t CFSR; /*Offset: 0x028 (R/W) Configurable Fault Status Register*/
__IO uint32_t HFSR; /*Offset: 0x02C (R/W) HardFault Status Register */
__IO uint32_t DFSR; /*Offset: 0x030 (R/W) Debug Fault Status Register*/
__IO uint32_t MMFAR; /*Offset: 0x034 (R/W) MemManage Fault Address Register*/
__IO uint32_t BFAR; /*Offset: 0x038 (R/W) BusFault Address Register*/