武汉理工大学《EDA》课程设计说明书
七 参考文献
[1] 潘松，黄继业.EDA技术与VHDL，第2版．北京：清华大学出版社，2007． [2] 陈小毛，胡机秀．新编数字电路与EDA技术．北京：国防工业出版社，2008． [3] 夏路易.基于EDA的电子技术课程设计．北京：电子工业出版社，2009． [4] 宋嘉玉，孙丽霞．EDA实用技术．北京：人民邮电出版社，2006. [5] 齐洪喜，陆颖．VHDL电路设计实用技术．北京：清华大学出版社，2004.
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武汉理工大学《EDA》课程设计说明书
附录
（一）1KHZ分频 library ieee;
use ieee.std_logic_1164.all; entity counter10000 is port(clk:in std_logic; q:out std_logic); end counter10000;
architecture behave of counter10000 is signal q0:std_logic; begin
process(clk)
variable count:integer range 0 to 10000; begin
if clk'event and clk='1' then
if count<10000 then count:=count+1; else q0<=not q0; count:=0; end if; end if; end process; q<=q0; end behave;
（二）100进制毫秒模块 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cntm100 is
port(cs,clk:in std_logic;
co:buffer std_logic;
s_10ms,s_100ms:buffer std_logic_vector(3 downto 0); clear:in std_logic); end ;
architecture behave of cntm100 is signal clock:std_logic; begin
process(clk)
variable count1:integer range 0 to 5; begin
if clk'event and clk='1' then
if count1<5 then count1:=count1+1; else clock<=not clock; count1:=0; end if;
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武汉理工大学《EDA》课程设计说明书
end if; end process;
process(clock,cs,clear) begin
if clear='0' then if cs='1' then
if clock'event and clock='1' then co<='0';
if s_10ms=9 then s_10ms<=(others=>'0');
if s_100ms=9 then s_100ms<=(others=>'0');co<=not co; else s_100ms<=s_100ms+1; end if;
else s_10ms<=s_10ms+1; end if; end if;
else s_10ms<=s_10ms;s_100ms<=s_100ms; end if;
else s_10ms<=(others=>'0');s_100ms<=(others=>'0'); end if;
end process; end behave;
（三）60进制秒模块 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cntm60miao is port(clk:in std_logic;
co:buffer std_logic;
s_1s,s_10s:buffer std_logic_vector(3 downto 0); clear:in std_logic); end ;
architecture behave of cntm60miao is begin
process(clk) begin
if clear='0' then
if clk'event and clk='1' then co<='0';
if s_1s=9 then s_1s<=(others=>'0');
if s_10s=5 then s_10s<=(others=>'0');co<=not co; else s_10s<= s_10s+1; end if;
else s_1s<= s_1s+1; end if;
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武汉理工大学《EDA》课程设计说明书
end if;
else s_1s<=(others=>'0');s_10s<=(others=>'0'); end if;
end process; end behave;
（四）60进制分模块 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cntm60fen is port(clk:in std_logic;
s_1min,s_10min:buffer std_logic_vector(3 downto 0); clear:in std_logic); end ;
architecture behave of cntm60fen is begin
process(clk) begin
if clear='0' then
if clk'event and clk='1' then
if s_1min=9 then s_1min<=(others=>'0');
if s_10min=5 then s_10min<=(others=>'0'); else s_10min<= s_10min+1; end if;
else s_1min<= s_1min+1; end if; end if;
else s_1min<=(others=>'0');s_10min<=(others=>'0'); end if;
end process; end behave;
（五）控制模块 library ieee;
use ieee.std_logic_1164.all; entity control is
port(s_10ms,s_100ms,s_1s,s_10s,s_1min,s_10min:in std_logic_vector(3 downto 0); choose:in std_logic_vector(2 downto 0);
y:out std_logic_vector(3 downto 0)); end ;
architecture behave of control is begin
process(choose)
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武汉理工大学《EDA》课程设计说明书
begin
case choose is
when \ when \ when \ when \ when \ when \ when others=>null; end case; end process; end behave;
（六）扫描模块 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cntm8 is
port (clk:in std_logic;
count:out std_logic_vector(2 downto 0)); end;
architecture one of cntm8 is signal q0:std_logic; begin
process(clk)
variable count1:integer range 0 to 30000; begin
if clk'event and clk='1' then
if count1<30000 then count1:=count1+1; else q0<=not q0; count1:=0; end if; end if; end process; process(q0)
variable CQI:std_logic_vector(2 downto 0); begin
if q0'event and q0='1' then
if CQI<5 then CQI:=CQI+1; else CQI:=(others=>'0'); end if; end if; count<=CQI; end process; end one;
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