基于FP GA的HDB3码的编码器与译码器设计（软件设计）
Plusbout : out
std_logic_vector(1 downto 0);---插“B”信号输入 End hdb3plusb;
Architecture behave of hdb3plusb is Signal parity : std_logic;
Signal startflag : std_logic_vector(2 downto 0); Signal hdb3plusbregh : std_logic_vector(4 downto 0); Signal hdb3plusbreg1 : std_logic_vector(4 downto 0); Begin
---对两个连续“V”之间的非“0”符号进行奇偶判断
---parity为“0”表示两个连续“V”之间的非“0”符号位偶数个，需要进行插“V”操作
--- parity为“1”表示两个连续“V”之间的非“0”符号位奇数个，不需要进行插“V”操作 Process(clk) Begin
If clk’event and clk=’1’ then If plusvin=”10” then Parity<=’0’;
Elsif plusvin=”01” then Parity<=not parity; End if; End if; End process;
---当两个连续“V”之间的非“0”符号为偶数个，进行插“B”操作 ---符号“B”由“11”来表示 Process(clk) Begin
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基于FP GA的HDB3码的编码器与译码器设计（软件设计）
If clk’event and clk=’1’ then
If(plusvin=”10”) and (parity=’0’) then; Hdb3plusbregh(4)<=’1’;
Hdb3plusbregh(3)<= hdb3plusbregh(4) Hdb3plusbregh(2)<= hdb3plusbregh(3)
Hdb3plusbregh(1)<=’1’;---如果需要插“B”,则改变去过第1位的值 Hdb3plusbregh(0)<= hdb3plusbregh(1) Hdb3plusbreg1(4)<=’0’;
Hdb3plusbreg1(3)<= hdb3plusbreg1(4); Hdb3plusbreg1(2)<= hdb3plusbreg1(3);
Hdb3plusbreg1(1)<=’1’;---如果需要插“B”，则改变去过第1位的值 Hdb3plusbreg1(0)<= hdb3plusbreg1(1); Else
Hdb3plusbregh<=plusvin(1) & hdb3plusbregh(4 downto 1); Hdb3plusbregl<=plusvin(0) & hdb3plusbregl(4 downto 1); End if; End if; End process; Process(clk) Begin
If clk’event and clk=’1’ then Plusbout(1)<=hdb3plusbregh(0); Plusbout(0)<=hdb3plusbregl(0); End if; End process; End process;
Library ieee;
Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity hdb3poled2s is
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基于FP GA的HDB3码的编码器与译码器设计（软件设计）
Port(clk : in std_logic;
Plusbin : in std_logic_vector(1 downt0 0); Plusout : out std_logic; Minusout : out std_logic)
End hdb3poled2s;
Architecture behave of hdb3poled2s is Signal parity :std_logic;
Signal com : std_logic_vector(2 downto 0); Begin
Com<=plusbin & parity; Process(clk) Begin
If clk’event and clk=’1’ then Case com is When “011”=> Plusout<=’0’; Minusout<=’1’;
Parity<=not parity;---出现“01”时，下次正/负电平信号发生交替 When “010”=> Plusout<=’1’; Minusout<=’0’;
Parity<=not parity;---出现“01”时，下次正/负电平信号发生交替 When “101”=> Plusout<=’1’; Minusout<=’0’;
Parity<=parity;---出现“10”时，下次正/负电平信号不发生交替 When “100”=> Plusout<=’0’; Minusout<=’1’;
Parity<=parity;--- 出现“10”时，下次正/负电平信号不发生交替
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基于FP GA的HDB3码的编码器与译码器设计（软件设计）
When “111”=> Plusout<=’1’ Minusout<=’1’;
Parity<=not parity;---出现时，下次正/负电平信号发生交替 When “110”=> Plusout<=’1’; Minusout<=’1’;
Parity<=not parity;---出现“11”时，下次正/负电平信号发生交替 When others=> Plusout<=’0’; Minusout<=’0’; Parity<=parity; End case; End if; End process; End behave;
B HDB3译码器的VHDL完整程序 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hdb3dec is port(clk:in std_logic; plusin : in std_logic; minusin : in std_logic; dataout : out std_logic;) end hdb3dec;
architecture behave of hdb3dec is
signal plusbuf : std_logic_vector(4 downto 0); signal minusbuf : std_logic_vector(4 downto 0); begin
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基于FP GA的HDB3码的编码器与译码器设计（软件设计）
process(clk)
if clk’event and clk=’1’ then
---判断出正极性出现“V”符号，则还原出4个连“0” if plusin=’1’ and plusbuf(4 downto 1)”0001” and minusbuf(4 downto 1)=”0000” then plusbuf<=”00001”;
minusbuf<=minusin & minusbuf(4 downto 1); ---判断出负极性出现“V”符号，则还原出4个连“0” Elsif minusin=’1’ and minusbuf(4 downto 1)=”0001” and plusbuf(4 downto 1)=”0000” then
plusbuf<=plusin & plusbuf(4 downto 1); minusbuf<=”00001”;
---判断出正极性出现“V”符号和“B”符号，则还原出4个连“0” Elsif plusin=’1’ and plusbuf(4 downto 2)=”001” And minusbuf(4 downto 2)=”000” then
Minusbuf<=minusin & minusbuf(4 downto 1); Plusbuf<=”0000” & plusbuf(1);
---判断出负极性出现“V”符号和“B”符号，则还原出4个连“0” Elsif minusin=’1’ and minusbuf(4 downto 2)=”001” And plusbuf(4 downto 2)=”000” then
Plusbuf<=plusin & plusbuf(4 downto 1); Minusbuf<=”0000” & minusbuf(1); ---其他情况保持不变
Else
Plusbuf<=plusin & plusbuf(4 downto 1); Minusbuf<=minusin & minusbuf(4 downto 1); End if; End if; End process;
---还原基带信号输出进程
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