RL A MOV 50H,A
MM5: MOV P2,50H
MOV DPTR,#TAB MOV A,45H ADD A ,#0AH MOVC A,@A+DPTR MOV P0 ,A LCALL YY MOV A,50H RL A MOV 50H,A
JNB P1.0,KK1 JNB P1.6,KK7 JNB P1.1,KK2 JNB P1.2,KK3 JNB P1.3,KK4 CJNE R0,#01H,HH1 JNB P1.4,KK5 SETB TR0
BB: JB TF0, GG
LJMP MM
KK5: JNB P1.4,KK5
MOV R0,#00H LJMP UU
HH1: JNB P1.5 ,KK6
LJMP UU
KK1： LJMP KKK1 KK7: LJMP KKK7
；按键判断程序 GG: CLR TF0
MOV A,47H CJNE A,#09H,LL1 MOV 47H,#00H MOV A,46H CJNE A,#09H,LL2 MOV 46H,#00H
KK4: JNB P1.3,KK4
JNB P3.1,QQ1 MOV A,45H CJNE A,#09H,QQ1 CLR P3.1
QQ1: MOV A,45H
CJNE A,#09H,LL3 MOV 45H,#00H MOV A,44H CJNE A,#05H,LL4 MOV 44H,#00H
KK3: JNB P1.2,KK3
MOV A,43H CJNE A,#09H,LL7 MOV 43H,#00H MOV A,42H CJNE A,#05H,LL8 MOV 42H,#00H
KK2: JNB P1.1,KK2
MOV A,41H CJNE A,#09H,LL5 MOV 41H,#00H
LL6: INC 40H
LJMP UU
KKK1: MOV A,#00H
MOV 40H,A MOV 41H,A MOV 42H,A MOV 40H,A MOV 43H,A MOV 44H,A MOV 45H,A LJMP MM
KKK7: MOV A,#00H
MOV 44H,A MOV 45H,A MOV 46H,A MOV 47H,A LJMP MM
KK6: JNB P1.5 ,KK6
MOV R0,#01H LJMP UU
LL1: INC 47H
LJMP UU
LL7: INC 43H
LJMP UU
LL8: INC 42H
LJMP UU
LL2: INC 46H
LJMP UU
LL3: INC 45H
LJMP UU
LL4: INC 44H
LJMP UU
LL5: CJNE A,#03H,DD1
MOV A,40H CJNE A,#02H,DD1 MOV 40H,#00H MOV 41H,#00H LJMP UU
DD1: INC 41H
LJMP UU
YY: MOV R6,#10 ；延时程序 YY1: MOV R7,#09 YY2 : NOP
NOP DJNZ R7,YY2 DJNZ R6,YY1 RET
TAB: DB 3FH,06H,5BH,4FH,66H,6DH,7DH,07H,7FH,67H
DB 0BFH,86H,0DBH,0CFH,0E6H,0EDH,0FDH,87H,0FFH,0E7H END
实验8：交通灯设计
一：设计一个十字路口交通灯控制系统，信号灯以红->绿->黄的顺序变化，红灯50秒，绿灯45秒，黄灯5秒。 时钟分频模块： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fp IS
PORT(clk:IN STD_LOGIC;
CLK1S:OUT STD_LOGIC); END fp;
ARCHITECTURE one OF fp IS
交通灯控制及计时模块： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY kz IS
PORT(CLK1S,car:IN STD_LOGIC;--1S脉冲，支干道车辆检测
TIME1H,TIME1L:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--支干道计时 TIME2H,TIME2L:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--支干道计时 count:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --系统总计时 led:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)); --交通灯显示 SIGNAL N: STD_LOGIC_VECTOR(9 DOWNTO 0); BEGIN PROCESS(clk)
BEGIN
IF clk'EVENT AND clk='1' THEN N<=N+1; END IF;
END PROCESS; CLK1S<=N(9); END one;
END KZ;
ARCHITECTURE one OF kz IS
TYPE states IS (s0,s1,s2,s3,s4,s5); --状态初始化 SIGNAL current_state,next_state :states; SIGNAL c:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN