sel:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --数码管位码 seg:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --数码管段码
END jtd;
ARCHITECTURE one OF jtd IS COMPONENT fP
PORT(clK:IN STD_LOGIC;
CLK1S:OUT STD_LOGIC);
END COMPONENT; COMPONENT kz
PORT(CLK1S,car:IN STD_LOGIC;
TIME1H,TIME1L:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); TIME2H,TIME2L:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); count:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); led:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END COMPONENT; COMPONENT xs
PORT(clK,CLK1S,car:IN STD_LOGIC;
TIME1H,TIME1L:IN STD_LOGIC_VECTOR(3 DOWNTO 0); TIME2H,TIME2L:IN STD_LOGIC_VECTOR(3 DOWNTO 0); count:IN STD_LOGIC_VECTOR(6 DOWNTO 0); sel:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); seg:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;
SIGNAL CLK1S:STD_LOGIC;
SIGNAL count:STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL TIME1H,TIME1L,TIME2H,TIME2L:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
U1:fp PORT MAP(CLK=>clk,CLK1S=>CLK1S); U2:
kz
PORT
MAP
(CLK1S=>CLK1S,car=>car,count=>count,led=>led,TIME1H=>TIME1H, TIME1L=>TIME1L,TIME2H=>TIME2H,TIME2L=>TIME2L); U3:
xs
PORT
MAP
(clk=>clk,CLK1S=>CLK1S,car=>car,count=>count,sel=>sel,seg=>seg, TIME1H=>TIME1H,TIME1L=>TIME1L,TIME2H=>TIME2H,TIME2L=>TIME2L) END;实验10：正弦信号发生器
设计一个正弦信号发生器，产生15KHz的正弦信号。(每周期取64个点)
1、 建立.mif格式文件 #include
int i; float s;
for(i=0;i<1024;i++) {
s=sin(atan(1)*8*i/256);
printf(\} }
将生成的sdata.mif 文件，再加上.mif文件的头部说明即可。 .mif文件的头部说明如下所示：
WIDTH=8; DEPTH=1024;
ADDRESS_RADIX=DEC; DATA_RADIX=DEC; CONTENT BEGIN 0:127; 1:130; 2:133; 3:136; 4:139; 5:143; 6:146;
……（数据略去） 64:319 END;
1）、源代码1如下所示： LIBRARY ieee;
USE ieee.std_logic_1164.all; LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all; ENTITY rom_1024 IS PORT
( address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END rom_64;
ARCHITECTURE SYN OF rom_64 IS
SIGNAL sub_wire0:STD_LOGIC_VECTOR(7 DOWNTO 0); COMPONENT altsyncram
intended_device_family : STRING; width_a : NATURAL; widthad_a : NATURAL; numwords_a : NATURAL;
operation_mode : STRING; outdata_reg_a : STRING; address_aclr_a : STRING; outdata_aclr_a : STRING; width_byteena_a : NATURAL; init_file : STRING; lpm_hint : STRING; lpm_type : STRING );
PORT ( -- altsyncram元件接口声明 clock0 : IN STD_LOGIC ;
address_a: IN STD_LOGIC_VECTOR (9 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP (
intended_device_family=>\
width_a => 8, --数据线宽度8 widthad_a => 10, --地址线宽度10 numwords_a => 64, --数据数量1024 operation_mode => \模式ROM
outdata_reg_a => \输出锁存CLOCK0 address_aclr_a => \无异步地址清0
outdata_aclr_a => \无输出锁存异步清0 width_byteena_a => 1, --byteena_a输出口宽度1
init_file => \初始化数据文件 lpm_hint => \ lpm_type => \类型 )
PORT MAP (
clock0 => clock,
address_a => address, q_a => sub_wire0 ); END SYN; 2）、顶层设计代码： library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity singt is
port(clk : in std_logic; --信号源时钟
dout : out std_logic_vector(7 downto 0)); --8位波形数据输出 end singt;
architecture dacc of singt is component rom_64
--调用波形数据存储器LPM_ROM, 文件:rom_64.vhd声明
port(address:in std_logic_vector(9 downto 0); --10位地址信号
clock : in std_logic; --地址锁存时钟
q:out std_logic_vector(7 downto 0)); end component;
signal q1:std_logic_vector(9 downto 0); --设内部节点作为地址计数器 begin
process(clk) --LPM_ROM地址发生进程 begin
if clk'event and clk='1' then
q1<=q1+1; --Q1作为地址发生器计数器 end if;
end process;
u1:rom_64 port map (address=>q1,q=>dout,clock=>clk); --end dacc;
例化