图6-29 自动布线
因为最初在PCB Board Wizard中确定我们的板是双面印刷电路板，用户可以使用顶层和底层进行手工布线。为此，从菜单中选择Tools>>Un-Route>>All，[快捷键：U，A]来取消布线 。和以前一样开始布线，在放置线的时候使用*键来切换层。 Altium Designer软件在切换层的时候会自动的插入必要的过孔。 注意 : 由自动布线器完成的布线将显示两种颜色：红色表示顶部信号层布线和蓝色表示底层信号层布线。可用于自动布线的信号层定义是符合 PCB Board Wizard 中的布线层设计规则约束。还要注意两个电源网络布线更宽的间隔符合两种线宽规则约束。不必担心，如果在你的布线设计不完全如上图所示的一样。器件摆放的位置将不会完全一样，也可能是不同的布线样式。
板设计数据校验
Altium Designer is a rules-driven board design environment, in which you can define many types of design rules to ensure the integrity of your board. Typically, you set up the design rules at the start of the design process and then verify that the design complies with the rules as you work through the design, and at the end of the design process.
Earlier in the tutorial we examined the routing design rules and added a new width constraint rule. We also noted that there were already a number of rules that had been created by the PCB Board Wizard, and that there were some existing design rule violations against these default rules.
Altium Designer支持多级设计规则约束功能。用户可以对同一个对象类设置多个规则，每条规则还可以限定约束对象的范围。规则优先级定义服从规则的先后次序。
为了校正电路板使之符合设计规则的要求，用户可以利用设计规则检查功能(DRC):
1. 选择 Design?Board Layers & Colors (快捷按键: L) 并确认复选项 Show 及 System Colors
区的DRC错误标记选项已被选取，这样DRC错误标记将被显示。
2. 选择 Tools?Design Rule Check (快捷按键: T, D)，打开 Design Rule Checker 对话窗口，使能
online 和 batch DRC 选项。
规则检测，Online和Batch均可以手工配置.
3. 鼠标点击窗口左边的 Report Options 图标，保留缺省状态下 Report Options 区域的所有选项，
并执行 Run Design Rule Check 命令按钮，随之将出现设计规则检测报告。并将同时弹出一个消息窗口。
4. 点击违例条款 Silkscreen over Component Pads ，用户将跳转到相应违例报告区域。 5. 点击违例条款 Silkscreen over Component Pads 的任一条记录，用户将跳转到PCB，并放大
显示出现违例的设计区域。注意，放大的倍数取决于在 System - Navigation 环境配置内的设置。
显示每项违例的细节，本例的丝印与焊盘的间隔少于10mil.
6. 显示每项违例的细节, 如上图所示。注意用户可以通过 View Configurations 窗口内的 DRC
Detail Markers 配置违例的图形显示颜色。
7. 需要找出所有实际违反丝印与焊盘间安全间距规则约束的对象，可以选择菜单
Reports?Measure Primitives 命令。注意，用户可以通过快捷功能按键 CTRL+G 修改电气栅格的值。如5mil。
8. To resolve this error we can either modify the footprint, increasing the separation, or we can edit
the design rule, decreasing the required separation. For this tutorial we will edit the design rule, to do this select Design?Rules from the menus to open the PCB Rules and Constraints Editor dialog.
9. In the Manufacturing category, open the Silkscreen Over Component Pads rule type, and
click on the existing rule.
10. Edit the Silkscreen Over Exposed Component Pads Clearance value, changing it from
10mil to 9mil.
These pads are closer than the 13mil specified in the Clearance Constraint design rule.
? 运用习惯上与检查晶体管上焊盘间的安全间距相同的技术，检查阻焊数据与焊盘之间的间隙。 Switch back to the PCB document and you will see that the transistor pads are highlighted in green, indicating a design rule violation.
1. Look through the errors list in the Messages panel. It lists any violations that occur in the PCB
design. Notice that there are four violations listed under the Clearance Constraint rule. The details show that the pads of transistors Q1 and Q2 violate the 13mil clearance rule. 2. Double-click on an error in the Messages panel to jump to its location on the PCB.
Normally you would set up the clearance constraint rules before laying out your board, taking account of routing technologies and the physical properties of the devices. Let's analyze the error then review the current clearance design rules and decide how to resolve this situation. 3. Open the PCB Rules and Constraints Editor dialog (Design?Rules). Expand the Electrical,
then the Clearance rule type. There will be one Clearance design rule, click on it to display its settings.
4. Note that this rule requires All objects to be away from All other objects, at least 13mil. Since
the clearance between the transistor pads is less than this, they generate a violation when we run a DRC.
5. We know that the minimum distance between the transistor pads is just over 10mil, so let's set
up a design rule that allows the clearance constraint of 10mil for the transistors only.
6. Select the Clearance type rule in the Design Rules folder on the left of the dialog, right-click on
it, then select New Rule to add a new clearance constraint rule. 7. Click on the new Clearance rule, Clearance_1. Change the Name to
Clearance_Transistors, and set the Minimum Clearance to 10mil in the
Constraints section.
8. The final task is to set the Scope, or Full Query for the rule. There are a number of ways the
rule could be scoped, the most appropriate in this case would be to target the rule to any component that uses the transistor footprint. To do that, select the Advanced (Query) option
(in the upper section of the dialog), then click the *Query Builder button to open the Building Query from Board dialog.
9. Click Condition/Type Operator dropdown to Add first condition, and select Associated with
Footprint from the list.
10. Set the Condition Value to BCY-W3/E4 (the footprint type being used by the transistor), then
click OK to close the dialog. The new design rule should look like the figure shown below.
Design rule to set the clearance for all components using a specific footprint.
11. Click OK to close the PCB Rules and Constraint Editor dialog. The online DRC will run
automatically, clearing the errors.
12. To confirm that the transistor pad clearance violations have been resolved, run the batch design
rule check again (Tools?Design Rule Check