LIN Network for Vehicle ApplicationsIssued 2004-08Revised 2005-09Superseding J2602-1 AUG2004
7.7.5 Bus Wiring Constraints.........................................................................................................31 7.7.6 Bus Wiring Practices to Improve EMC Performance...........................................................32 7.7.7 Bus Wiring Harness and ECU Connectors..........................................................................32 7.8 ESD Immunity......................................................................................................................32 7.9 EMC Testing Requirements.................................................................................................32 7.10 Fault Tolerant Modes...........................................................................................................32 7.11 Ground Offset Voltage.........................................................................................................33 7.12 Operating Battery Power Voltage Range.............................................................................33 7.12.1 Normal Battery Voltage Power Operation............................................................................33 7.12.2 Battery Power Over-Voltage Operation...............................................................................33 7.12.3 Low Battery Voltage Operation............................................................................................34 7.12.4 Battery Offset Voltage..........................................................................................................34 7.12.5 Reverse Battery Blocking Diode..........................................................................................34 7.13 Environmental Requirements...............................................................................................34 7.13.1 Transmit Operating Conditions............................................................................................34 7.13.1.1 Master Device......................................................................................................................34 7.13.1.2 Slave Device........................................................................................................................34 7.13.1.2.1 Stand-Alone Transceivers....................................................................................................34 7.13.1.2.2 Integrated Transceivers.......................................................................................................34 8. Validation..............................................................................................................................34
9. Notes....................................................................................................................................35 9.1 Marginal Indicia....................................................................................................................35
List of Tables Table 1 NAD to Message ID Mapping..............................................................................................15 Table 2 Common Signal Encoding Type Mapping to LIN Defined Data Entities..............................19 Table 3 ERR States...........................................................................................................................20 Table 4 Master-Slave Communication Clock Tolerance...................................................................24 Table 5 Master-Slave Communication Clock Tolerance...................................................................24 Table 6 LIN Bus Signals and Loading Requirements.......................................................................25 Table 7 #Nodes/Network Resistance/Master Node Capacitance vs. Max Wire Length Chart.........31 Table 8 ESD Immunity Requirements...............................................................................................32
List of Figures Figure 1 Wake-up Signal Timing........................................................................................................23 Figure 2 Bit Sample Timing................................................................................................................26 Figure 3 Typical LIN Slave Bus Interface...........................................................................................27 Figure 4 Typical LIN Master Bus Interface.........................................................................................27 Figure 5 LIN Ring Topology...............................................................................................................29 Figure 6 LIN Linear Topology.............................................................................................................30 Figure 7 LIN Star Topology................................................................................................................30 Figure 8 LIN Combination Ring and Star Topology...........................................................................30 Figure E1 Relation Between Propagation Delay and Duty Cycle........................................................44