EM78P372N数据手册
EM78P372N8-Bit Microcontroller6.1.4 R3 (Status Register)Bit 7 RST Bit 6 IOCS Bit 5 Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 CBit 7 (RST): Bit of reset type Set to “1” if wake-up from sleep on pin change, comparator status change, or AD conversion completed. Set to “0” if wake-up from other reset types. Bit 6 (IOCS): Select the Segment of IO control register 0: Segment 0 (IOC50 ~ IOCF0) selected 1: Segment 1 (IOC51 ~ IOCC1) selected Bit 5: Not used, set “0” at all the time. Bit 4 (T): Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during power on, and reset to “0” by WDT time-out (for more details, see Section 6.5.2, The T and P Status under Status Register). Bit 3 (P): Power-down bit. Set to “1” during power-on or by a "WDTC" command and reset to “0” by a "SLEP" command (see Section 6.5.2, The T and P Status under Status Register for more details). Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag6.1.5 R4 (RAM Select Register)Bit 7 (SBANK): Special Register 0x05~0x0F bank selection bit. Bit 6 (BANK): Used to select Bank 0 or Bank 1 of the register Bits 5 ~ 0: Used to select a register (Address: 00~0F, 10~3F) in indirect addressing mode. See the table under Section 6.1.3.1 Data Memory Configuration.Product Specification (V1.1) 05.24.2011(This specification is subject to change without further notice) 9