基于FPGA的多功能波形发生器
课程设计实验报告
学院： 电气与控制工程学院 班级： 微电子1101 学号： 1106080118 姓名： 李少飞 日期： 2015.4.2
一、电路主体电路图 二、各模块vhdl代码 三、各模块仿真结果 四、实验感悟
一、实验主体电路
二、各模块
vhdl代码
三角
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf; USE altera_mf.all;
ENTITY sanjiao IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );
END sanjiao;
ARCHITECTURE SYN OF sanjiao IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( clock0 : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT;
BEGIN q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => \ clock_enable_output_a => \ init_file => \ intended_device_family => \ lpm_hint => \ lpm_type => \ numwords_a => 256, operation_mode => \ outdata_aclr_a => \ outdata_reg_a => \ widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( clock0 => inclock, address_a => address, q_a => sub_wire0 );
END SYN;
-正弦
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf; USE altera_mf.all;
ENTITY sinx IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END sinx;
ARCHITECTURE SYN OF sinx IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( clock0 : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT;
BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => \ clock_enable_output_a => \ init_file => \ intended_device_family => \ lpm_hint => \ lpm_type => \ numwords_a => 256, operation_mode => \ outdata_aclr_a => \ outdata_reg_a => \