widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( clock0 => inclock, address_a => address, q_a => sub_wire0 );
END SYN; 方波
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf; USE altera_mf.all;
ENTITY fangbo IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );
END fangbo;
ARCHITECTURE SYN OF fangbo IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING;
numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( clock0 : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT;
BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => \ clock_enable_output_a => \ init_file => \ intended_device_family => \ lpm_hint => \ lpm_type => \ numwords_a => 256, operation_mode => \ outdata_aclr_a => \ outdata_reg_a => \ widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( clock0 => inclock, address_a => address, q_a => sub_wire0 );
END SYN; 斜波
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf; USE altera_mf.all;
ENTITY xiebo IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );
END xiebo;
ARCHITECTURE SYN OF xiebo IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( clock0 : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT;
BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => \ clock_enable_output_a => \ init_file => \ intended_device_family => \ lpm_hint => \ lpm_type => \ numwords_a => 256, operation_mode => \ outdata_aclr_a => \ outdata_reg_a => \ widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( clock0 => inclock, address_a => address, q_a => sub_wire0 );
END SYN; 四选一 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity choice_4 is
port(sel:in std_logic_vector(1 downto 0);
d1,d2,d3,d4:in std_logic_vector(7 downto 0); q:out std_logic_vector(7 downto 0)); end choice_4;
architecture behave of choice_4 is begin
process(sel) begin case sel is
when \
when \when \when \when others=>null; end case; end process; end architecture; 2-4译码器
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY decoder24 IS
PORT(sel:IN std_logic_vector(1 downto 0); en1,en2,en3,en4:OUT std_logic); END;
ARCHITECTURE be OF decoder24 IS BEGIN process(sel) BEGIN
case sel is
when \ when \ when \ when \ when others=>null; end case; END process; END;
正选扫描电路 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; --正弦信号发生器源文件 USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY sins IS
PORT ( CLK,en ,reset: IN STD_LOGIC; --信号源时钟
DOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );--8位波形数据输出 END sins;
ARCHITECTURE behave OF sins IS
COMPONENT sinx --调用波形数据存储器LPM_ROM文件：datarom.vhd声明 PORT(address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);--8位地址信号 inclock : IN STD_LOGIC ;--地址锁存时钟
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT;
SIGNAL Q1 : STD_LOGIC_VECTOR (7 DOWNTO 0); --设定内部节点作为地址计数器