面向多相机接入的TMS320C6678图像处理系统硬件说明
DSPA_HOUT DSPA_BOOTCOMPLETE DSPA_SYSCLKOUT DSP_PORZ DSP_RESETFULLZ DSP_RESETZ Clock Generation: CDCL6010_LOCK CDCL6010_SDA CDCL6010_SCL Power Sequences Control : I I I O O O I O O DSP HOUT DSP Boot Complete Indication DSP System Clock Output DSP Power-On Reset DSP Full Reset DSP Reset LVCMOS status signaling. SDA/SCL bidirectional serial data SDA/SCL serial clock 0.75V Voltage Power Supply Enable : DSPA_VCC0V75_EN O DSPA_VCC0V75_EN is for 0.75V power plane control. 1.0V Voltage Power Supply Enable: VCC1V0_EN O VCC1V0_EN is for 1.0V power plane control. CVDD Voltage Power Supply Enable: CVDD_EN O CVDD_EN is for CVDD power plane control. 1.5V Voltage Power Supply Enable: VCC1V5_INH O VCC1V5_EN is for 1.5V power plane control. 1.8V Voltage Power Supply Enable: VCC1V8_EN O VCC1V8_EN is for 1.8V power plane control. 1.5V Voltage Power Good Indication: VCC1V5_PGOOD I This signal indicates the 1.5V power is valid. 1.0V Voltage Power Good Indication: VCC1V0_PGOOD I This signal indicates the 1.0V power is valid. CVDD Voltage Power Good Indication: CVDD_PGOOD I This signal indicates the CVDD power is valid. 面向多相机接入的TMS320C6678图像处理系统硬件说明
System Power Good Indication: This SYS_PGOOD I signal is indicated by the FPGA to the system when all the power supplies are valid. RESET Buttons and Requests : FULL_RESET I Full Reset Button Input: This button input is used to initiate a Full Reset event. Warm Reset Button Input: This button WARM_RESET I input is used to initiate a Warm Reset event. COLD_RESET (RFU) I Cold Reset Button Input: Reserved for Future Use (RFU). Reset Request from the DSP Emulator TRGRSTZ I Header: A warm Reset sequence will be initiated if an active TRGRSTZ event is recognized by the FPGA. DEBUG LED: Debug LED: The LEDs are used for DEBUG_LED[0:3] FPGA Storage (RFU): FPGA_SPI_CS# FPGA_SPI_SI FPGA_SPI_SCK FPGA_SPI_SO DSP SPI : DSP SPI Serial Data MISO: This signal is connected to the TMS320C6678 DSP DSPA_SSPMISO O SPIDIN pin. This signal is used for serial data transfers from the slave (FPGA) output to the master (DSP) input in the DSP_SSPCS1 asserted period. O O O I FPGA SPI Chip Select : (RFU) FPGA SPI Serial Data MOSI : (RFU) FPGA SPI Clock Output : (RFU) FPGA SPI Serial Data MISO : (RFU) O debugging purposes only. It can be configured by the registers in the FPGA. 面向多相机接入的TMS320C6678图像处理系统硬件说明
DSP SPI Chip Select 1: This signal is connected to the TMS320C6678 DSP DSPA_SSPCS1 I SPISCS1 pin. The falling edge of the SSPCS1 from the DSP will initiate a transfer. If SSPCS1 is high, no data transfer can take place. DSP SPI Serial Data MOSI: This signal is connected to the DSP SPIDOUT pin. This DSPA_SSPMOSI I signal is used for serial data transfers from the master (DSP) output to the slave (FPGA) input. DSP SPI Serial Clock: The FPGASPI FPGA_SSPCK I bus clocks data in on the falling edge of SSPCK. Data transitions therefore occur on the rising edge of the clock. PHY Interface : PHY_INT# I Interrupt Request from 88E111 PHY (RFU) Reset to 88E1111 PHY: This signal is used to reset the 88E1111 PHY device. The PHY_RST# will be asserted during PHY_RST# O the active DSP_PORZ or DSP_RESETFULLZ period. The PHY_RST# logic also can be configured by the DSP accessed register. FMC GPIO FMC_GPIO_P/N[0:21] FPGA_TCK FPGA_TDO FPGA_TDI FPGA_TMS Miscellaneous: MAIN_48MHZ_CLK_R I FPGA Main Clock Source: A 48 MHz clock is used as the FPGA main clock O, Diff User defined differential signals I O I I FPGA JTAG Clock Input FPGA JTAG Data Output FPGA JTAG Data Input FPGA JTAG Mode Select Input FPGA JTAG TAP Control Port: 面向多相机接入的TMS320C6678图像处理系统硬件说明
source. DSP Timer 0 Clock: The FPGA provides a 24MHz clock to the DSP timer 0 input. DSPA_TIMI0 O During the IISC-6678 Board Power-on or RESETFULLZ asserted period, the FPGA will drive the PCIESSEN switch state to DSP for latching. NAND Flash Write Protect: This signal is NAND_WP# O used to control the NAND flash write-protect function. NOR Flash Write Protect: This signal is NOR_WP# O used to control the NOR flash write-protect function. EEPROM Write Protect: This signal is EEPROM_WP O used to control the EEPROM write-protect function. PCIESSEN USER_Define[0:2] FPGA_IO[1:6] FPGA Mode FPGA_M[0:2] I Mode Select. Selects the FPGA configuration mode. Variant Select. Instructs the FPGA how to FPGA_VS[0:2] I communicate with the attached SPI Flash PROM. FPGA Configuration Done. Low during FPGA_DONE I/O configuration. Goes High when FPGA successfully completes configuration. Program FPGA. Active Low. When FPGA_PROG I asserted low for 500 ns or longer, forces the FPGA to restart its configuration process by clearing configuration memory I I I/O PCIE Subsystem Enable: This is used for the PCIESSEN switch input. User Defined Switch: This is reserved for the user defined switch input. Extend IO 面向多相机接入的TMS320C6678图像处理系统硬件说明
and resetting the DONE and INIT_B pins once PROG_B returns High. 5.3 操作顺序
本小节描述FPGA的操作顺序，它包含： 5.3.1 上电时序 5.3.2 掉电时序
5.3.1 上电时序
以下提供了FPGA上电时序的详细步骤：
? 在板卡3.3V电压稳定以及FPGA设计代码被加载后，FPGA就进入上电时序
操作；
? FPGA开始上电时序操作，进入IDLE状态，等待10ms后，开启DSPA_CVDD
（CVDD_EN拉高）；
? DSPA_CVDD稳定后（即CVDD_PGOOD信号有效）等待5ms，开启VCC1V0
DSP核电压；
? VCC1V0 DSP核电压稳定后，等待5ms开启1.8V电压；
? 1.8V稳定后，启动CDCL6010的配置，同时等待5ms后开启1.5V电压； ? 1.5V稳定后，等待5ms后开启0.75V电压；
? 0.75V电压稳定后，等待5ms，检测CDCL6010_LOCK的状态，在CDCL6010
的 锁 相 环 状 态 稳 定 后，FPGA 将 拉 高DSP_RESETz 和DSPA_LRESETz并且使得DSP_PORz和DSP_RESETFULLz保持有效； ? 在拉高DSP_RESETz和DSPA_LRESETz后，等待5ms，FPGA拉高DSP_PORz
并且依然保持DSP_RESETFULLz有效。再等待5ms，FPGA 将拉高DSP_RESETFULLz。在RESETSTAT#被拉高的这段时间内，DSP采样接在FPGA上的拨码开关值进行引导模式配置。FPGA也将把PCIESSEN开关值传输给DSP_TIMI0用于DSP引导模式配置； ? 等待DSP的RESETSTAT#信号从低到高； ? 至此IISC-6678板卡的上电时序完成。
5.3.2 掉电时序
以下描述了FPGA掉电时序的详细步骤：
? 一旦系统上电后，如果有任何电源故障发生，将会触发FPGA去进行掉电时
序操作。
? 一旦被拉低的POWER GOOD信号被FPGA检测到，FPGA将立马把
DSP_PORz和 DSP_RESETFULLz信号发送给DSP。
? 等待5ms，FPGA将通过使能引脚把所以的系统电源全部关掉并且通过掉电