if(flag ==0) cpld_ctrl_back &= ~B7_MSK; else cpld_ctrl_back |= B7_MSK; CPLD_CTRL_REG = cpld_ctrl_back; }
//----------------------------------------------------------------
void SCLK_DIN23(unsigned int flag_clk,unsigned int flag_din,unsigned int flag_din_en) { if(flag_clk==0) cpld_ctrl_back &= ~B5_MSK; else cpld_ctrl_back |= B5_MSK; if(flag_din==0) cpld_ctrl_back &= ~B6_MSK; else cpld_ctrl_back |= B6_MSK; if(flag_din_en == 0) cpld_ctrl_back &= ~B7_MSK; else cpld_ctrl_back |= B7_MSK; CPLD_CTRL_REG = cpld_ctrl_back; }
//---------------------------------------------------------------- void set_aic23_sci_mode() {
// AIC23_CS(0); AIC23_DIN_EN(1); AIC23_DIN(1); AIC23_CLK(1); delayMs_SYS(3); AIC23_DIN_EN(1); AIC23_DIN(1); delayMs_SYS(10); }
//---------------------------------------------------------------- void send_aic23_bit(unsigned int dat) { delayMs_SYS(2); SCLK_DIN23(0,dat,1); delayMs_SYS(2); AIC23_CLK(1);
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}
//----------------------------------------------------------------
void send_aic23_ctrl_reg(unsigned int dat) { unsigned int temp_dat; unsigned int flag; AIC23_CLK(1); delayMs_SYS(3); AIC23_DIN_EN(1); AIC23_DIN(1); delayMs_SYS(10); AIC23_DIN(0); //start delayMs_SYS(3); AIC23_CLK(0); delayMs_SYS(3); //SEND ADDRESS temp_dat = (AIC23_ADDR | 0x00); //write only { flag = 0x80; AIC23_DIN((flag & temp_dat)); delayMs_SYS(2); AIC23_CLK(1); for(flag = 0x40;flag != 0;flag >>=1) { send_aic23_bit(flag & temp_dat); } } SCLK_DIN23(0,0,0); delayMs_SYS(2); AIC23_CLK(1); delayMs_SYS(2); //ack AIC23_CLK(0); //是否需要同时输出 SDIN //SEND HIGNT BYTE temp_dat = (dat >> 8); { flag = 0x80; SCLK_DIN23(0,(flag & temp_dat),1);
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}
delayMs_SYS(2); AIC23_CLK(1); for(flag = 0x40;flag != 0;flag >>=1) { send_aic23_bit(flag & temp_dat); } }
SCLK_DIN23(0,0,0); delayMs_SYS(2); AIC23_CLK(1); delayMs_SYS(2); //ack AIC23_CLK(0); //是否需要同时输出 SDIN
//SEND LOW BYTE temp_dat = dat; { flag = 0x80; SCLK_DIN23(0,(flag & temp_dat),1); delayMs_SYS(2); AIC23_CLK(1); for(flag = 0x40;flag != 0;flag >>=1) { send_aic23_bit(flag & temp_dat); } }
SCLK_DIN23(0,0,0); delayMs_SYS(2); AIC23_CLK(1); delayMs_SYS(2); //ack AIC23_CLK(0); //是否需要同时输出 SDIN
AIC23_DIN(0); AIC23_DIN_EN(1); delayMs_SYS(2);
AIC23_CLK(1); delayMs_SYS(1); AIC23_DIN(1);
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void reset_aic23() {
send_aic23_ctrl_reg(0x1e00); //REG10 RESET AIC23 delayUs_SYS(100); }
void initial_aic23(void) { set_aic23_sci_mode(); reset_aic23();
send_aic23_ctrl_reg(0x0117); //REG0 Left line input channel volume control //send_aic23_ctrl_reg(0x0110); //REG0 Left line input channel volume control asm(\ //Address (bits 15-9) 0000000
//LRS (bits 8) 1 Left/right line simultaneous volume/mute update Enabled
//LIM (bits 7) 0 Left line input mute 0 = Normal
//XX (bits 6-5) 00 Reserved //LIV[4:0] (bits 4-0) 10111 Left line input volume control (10111 = 0 dB default)
//-----0000 0001 0001 0111
send_aic23_ctrl_reg(0x0317); //REG1 Right Line Input Channel Volume Controlxxxxxxxx
//send_aic23_ctrl_reg(0x0310); //REG1 Right Line Input Channel Volume Controlxxxxxxxx
asm(\ //Address (bits 15-9) 0000001
//RRS (bits 8) 1 Left/right line simultaneous volume/mute update Enabled
//RIM (bits 7) 0 Left line input mute 0 = Normal
//XX (bits 6-5) 00 Reserved
//RIV[4:0] (bits 4-0) 10111 Left line input volume control (10111 = 0 dB default)
//-----0000 0011 0001 0111
//send_aic23_ctrl_reg(0x05f9); //REG2 Left Channel Headphone Volume Control send_aic23_ctrl_reg(0x043f);
asm(\ //Address (bits 15-9) 0000010
//LRS (bits 8) 1 Left/right headphone channel simultaneous volume/mute update 1 = Enabled
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//LZC (bits 7) 1 Left-channel zero-cross detect 0 = Off
//LHV[6:0] (bits 6-0) 1111001 Left Headphone volume control (1111001 = 0 dB default)
//-----0000 0101 1111 1001
//send_aic23_ctrl_reg(0x07f9); //REG3 Right Channel Headphone Volume Control send_aic23_ctrl_reg(0x0670); //REG3 Right Channel Headphone Volume Control asm(\ //Address (bits 15-9) 0000011
//RLS (bits 8) 1 Left/right headphone channel simultaneous volume/mute update 1 = Enabled
//RZC (bits 7) 1 Left-channel zero-cross detect 0 = Off
//RHV[6:0] (bits 6-0) 1111001 Left Headphone volume control (1111001 = 0 dB default)
//-----0000 0111 1111 1001
// mcbsp2_write_rdy(0x0810); //选择线性输入
//send_aic23_ctrl_reg(0x0814); //选择麦克风输入 send_aic23_ctrl_reg(0x0815); //选择麦克风输入
asm(\ //REG4 Analog Audio Path Control //Address (bits 15-9) 0000100
//X (bits 8) 0 Reserved
//STA[1:0] (bits 7-6) 00 Sidetone attenuation 00 = –6 dB
//STE (bits 5) 0 Sidetone enable 0 = Disabled
//DAC (bits 4) 1 DAC select 1 = DAC selected
//BYP (bits 3) 0 Bypass 0 = Disabled 1=Enabled,ONLY FOR TEST
//INSEL (bits 2) 0 Input select for ADC 0 = Line
//MICM (bits 1) 0 Microphone mute 0 = Normal
//MICB (bits 0) 0 Microphone boost 0=OdB
//-----0000 1000 0001 0000
send_aic23_ctrl_reg(0x0A01); //REG5 Digital Audio Path Control //send_aic23_ctrl_reg(0x0A05); //REG5 Digital Audio Path Control asm(\ //Address (bits 15-9) 0000101
//X (bits 8-4) 00000 Reserved
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