//DACM (bits 3) 0 DAC soft mute 0 = Disabled
//DEEMP[1:0] (bits 2-1) 00 De-emphasis control 00 = Disabled
//ADCHP (bits 0) 1 ADC high-pass filter 1 = Enabled
//----- 0000 1010 0000 0001
send_aic23_ctrl_reg(0x0C00); //REG6 Power Down Control //send_aic23_ctrl_reg(0x0C01); //REG6 Power Down Control asm(\ //Address (bits 15-9) 0000110
//X (bits 8) 0 Reserved
//OFF (bits 7) 0 Device power 0 = On
//CLK (bits 6) 0 Clock 0 = On //OSC (bits 5) 0 Oscillator 0 = On
//OUT (bits 4) 0 Outputs 0 = On
//DAC (bits 3) 0 DAC 0 = On //ADC (bits 2) 0 ADC 0 = On //MIC (bits 1) 0 Microphone input 0 = On
//LINE (bits 0) 0 Line input 0 = On
//----- 0000 1100 0000 0000
send_aic23_ctrl_reg(0x0E73); //REG7 Digital Audio Interface Format asm(\ //Address (bits 15-9) 0000111
//X (bits 8-7) 00 Reserved
//MS (bits 6) 1 Master/slave mode 1 = Master
//LRSWAP (bits 5) 1 DAC left/right swap 1 = Enabled
//LRP (bits 4) 1 DAC left/right phase,1 = Right channel on, LRCIN low; \mode\1 = MSB is available on 2nd BCLK rising edge after LRCIN rising edge
//IWL[1:0] (bits 3-2) 00 Input bit length 00 = 16 bit
//FOR[1:0] (bits 1-0) 11 Data format 11 = DSP format, frame sync followed by two data words //----- 0000 1110 0111 0011
//send_aic23_ctrl_reg(0x108C); //8KHZ采样频率
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send_aic23_ctrl_reg(0x101C); //96KHZ采样频率
//REG8 Sample Rate Control asm(\ //Address (bits 15-9) 0001000
//X (bits 8) 0 Reserved //CLKOUT (bits 7) 0 Clock input divider 0 = MCLK
//CLKIN (bits 6) 0 Clock output divider 0 = MCLK
//SR[3:0] (bits 5-2) 0011 MCLK = 12.288 MHz, sampling rates=8KHZ
//BOSR (bits 1) 0 Base oversampling rate Normal mode: 0 = 256 fs
//USB/Normal(bits 0) 0 Clock mode select: 0 = Normal
//----- 0001 0000 0000 1100
send_aic23_ctrl_reg(0x1201); //REG9 Digital Interface Activation asm(\ //Address (bits 15-9) 0001001
//X (bits 8-1) 00000000 Reserved //ACT (bits 0) 1 Activate interface 1 = Active }
//--------------------结束---------------------------------------- 3、初始化程序 .asg #6c00h, EBSR .asg #07fdh, SYSR .asg #0800h,EGCR .asg #0801h,EMIRST .asg #0802h,EMIBE .asg #0803h,CE01 .asg #0804h,CE02 .asg #0805h,CE03 .asg #0806h,CE11 .asg #0807h,CE12 .asg #0808h,CE13 .asg #0809h,CE21 .asg #080ah,CE22 .asg #080bh,CE23 .asg #080ch,CE31 .asg #080dh,CE32 .asg #080eh,CE33
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.asg #080fh,SDC1 .asg #0810h,SDPER .asg #0811h,SDCNT .asg #0812h,INIT .asg #0813h,SDC2 .asg #0814h,SDC3
.asg #3400h, IODIR .asg #3401h, IODATA .asg #0001h, ICR .asg #0002h, ISTR
.text
.cpl_off_ke .macro .cpl_off bit(st1,#14)= 0 .endm
.cpl_on_ke .macro .cpl_on bit(st1, #14) = 1 .endm .def _initial_sys _initial_sys:
************ initial the state register ********************************* *port(IODATA)= #1fh *port(IODIR) = #70h *port(IODATA)= #1fh bit(st1, #13) = #1 xar0=#0h nop ar0=#02h *ar0=#3800h ar0+=#1 *ar0=#6100h xdp=#0 ar0=*abs16(#01h) ar0=*abs16(#46h)
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bit(st1,#11)=#1 bit(st1,#10)=#0 bit(st1,#7)=#0 bit(st1,#9)=#0 bit(st1,#8)=#0 xar0=#0 nop *ar0=#0
frequencySet_pll: ar3=#1c00h *port(#1c00h) = #2610h
again_pll_sub: tc1=bit(*ar3,#0) || readport() if(!tc1) goto again_pll_sub *port(#7fdh)=#000b *port(EBSR)=#9a01h *port(ICR) = #002fh *port(SYSR)=#0000h *port(EMIRST)=#0ffffh ar0=*port(EGCR) bit(ar0,@#5)=#0 *port(EGCR)=ar0 ar0=*port(EGCR) bit(ar0, @#9)=#1 bit(ar0, @#10)=#0 bit(ar0, @#11)=#0 *port(EGCR)=ar0 ar0=*port(EGCR) bit(ar0, @#4)=#1 *port(EGCR)=ar0 repeat(#5) nop
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*port(CE01)=#1313h *port(CE02)=#011bh *port(CE03)=#0000h *port(CE11)=#151fh *port(CE12)=#0f75fh *port(CE13)=#0000h *port(CE21)=#3000h *port(CE23)=#0000h *port(CE31)=#3000h *port(CE33)=#0000h *port(SDC1)=#2111h *port(SDPER)=#03e8h *port(SDC2)=#0222h ar0=*port(SDC3) bit(ar0, @#2)=#0 *port(SDC3)=ar0 ar0=*port(EGCR) bit(ar0, @#5)=#1 *port(EGCR)=ar0 repeat(#20) nop_16 *port(INIT)=#0000h repeat(#20) nop_16
*************************************************************** ar0=#49h *ar0=#0002h ar0+=#1 *ar0=#0002h xar0=#0 nop nop *ar0=#0 ar1=*ar0 bit(ar1,@#9)=#0
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