sub_in x yf_suber sub_outsub_in x ysub_in x ysub_in x yef_suber sub_outff_suber sub_outgf_suber sub_outu4diffr4LIBRARY IEEE ;
u5diffr5diffr6u6diffr7u7 sub_out
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY 8f_suber IS
PORT ( x0,x1,x2,x3,x4,x5,x6,x7 : IN STD_LOGIC ;
y0,y1,y2,y3,y4,y5,y6,y7 : IN STD_LOGIC ; sub_in : IN STD_LOGIC ;
sub_out : OUT STD_LOGIC ;
diffr0,diffr1,diffr2,diffr3 : OUT STD_LOGIC ; diffr4,diffr5,diffr6,diffr7 : OUT STD_LOGIC ) ;
END ENTITY 8f_suber ;
ARCHITECTURE 8fhd1 OF 8f_suber IS COMPONENT f_suber IS PORT ( x,y,sub_in : IN STD_LOGIC ; sub_out ,diffr : OUT STD_LOGIC ) ; END COMPONENT f_suber ; SIGNAL a,b,c,d,e,f,g : STD_LOGIC ; BEGIN
u0 : f_suber PORT MAP ( x=>x0, y=>y0, sub_in=>, sub_out=>a, diff=>diff0 ) ; u1 : f_suber PORT MAP ( x=>x1, y=>y1, sub_in=>a, sub_out=>b, diff=>diff1 ) ; u2 : f_suber PORT MAP (x=>x2, y=>y2, sub_in=>b, sub_out=>c, diff=>diff2 ) ;
u3 : f_suber PORT MAP (x=>x3, y=>y3, sub_in=>c, sub_out=>d, diff=>diff3 ) ; u4 : f_suber PORT MAP (x=>x4, y=>y4, sub_in=>d, sub_out=>e, diff=>diff4 ) ; u5 : f_suber PORT MAP (x=>x5, y=>y5, sub_in=>e, sub_out=>f, diff=>diff5 ) ; u6 : f_suber PORT MAP (x=>x6, y=>y6, sub_in=>f, sub_out=>g, diff=>diff6 ) ; u7 : f_suber PORT MAP (x=>x7, y=>y7, sub_in=>g, sub_out=> sub_out, diff=>diff7 ) ; END ARCHITECTURE 8fhd1 ; 3-5 程序：
或非门逻辑描述： LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY nor IS
PORT ( d, e : IN STD_LOGIC ; f : OUT STD_LOGIC ) ;
END ENTITY nor ;
ARCHITECTURE one OF nor IS BEGIN
f <= NOT ( d OR e ) ; END ARCHITECTURE one ;
时序电路描述： LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY circuit IS
PORT ( CL, CLK0 : IN STD_LOGIC ; OUT1 : OUT STD_LOGIC ) ; END ENTITY circuit ;
ARCHITECTURE one OF circuit IS COMPONENT DFF1 IS PORT ( CLK : IN STD_LOGIC ; D : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END COMPONENT DFF1 ; COMPONENT nor IS PORT ( d, e : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END COMPONENT nor ; COMPONENT not IS PORT ( g : IN STD_LOGIC ; h : OUT STD_LOGIC ) ; END COMPONENT not ; SIGNAL a, b : STD_LOGIC ; BEGIN
u0 : nor PORT MAP ( d=>b, e=>CL, f=>a ) ;
u1 : DFF1 PORT MAP ( CLK=>CLK0, D=>a, Q=>b ) ; u2 : not PORT MAP ( g=>b, h=>OUT1 ) ; END ARCHITECTURE one ; 3-6 LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY MX3256 IS
PORT( INA,INB,INCK,INC: IN STD_LOGIC ; E,OUT1: OUT STD_LOGIC) ; END ENTITY MX3256;
ARCHITECTURE one OF MX3256 IS COMPONENT LK35 IS
PORT ( A1,A2,CLK: IN STD_LOGIC ; O1,O2: OUT STD_LOGIC) ; END COMPONENT LK35; BEGIN 3-7
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_unsigned.ALL ; ENTITY CNT IS
PORT( CLK,EN,RST,opcode: IN STD_LOGIC ;
CQ: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; COUT: OUT STD_LOGIC) ; END ENTITY CNT;
ARCHITECTURE behav1 OF CNT IS BEGIN
PROCESS( RST,EN,CLK,opcode )
VARIABLE CQI: STD_LOGIC_VECTOR( 15 DOWNTO 0) ; begin
IF RST=?1? THEN CQI:=( OTHERS=>?0?) ; ELSIF EN=?1? THEN
IF CLK?EVENT AND CLK=?1? THEN CASE opcode IS
WHEN ?0? =>CQI:=CQI+1; WHEN ?1? =>CQI:=CQI-1;
WHEN OTHERS =>NULL; END CASE; END IF; END IF;
CASE opcode IS
WHEN ?0? => IF CQI=65535 THEN COUT<=?1?; ELSE COUT<=?0?; END IF;
WHEN ?1? => IF CQI=0 THEN COUT<=?1?; ELSE COUT<=?0?; END IF; WHEN OTHERS =>NULL; END CASE; CQ<=CQI; END PROCESS; END behav1; 3-8 3-9 3-10 3-11 3-12 3-13 3-14 程序1：
SIGNAL A,EN : STD_LOGIC ; PROCESS ( A, EN )
VARIABLE B : STD_LOGIC ; BEGIN
IF EN = ?1? THEN B := A ;
END IF ; END PROCESS ;
程序2：
ARCHITECTURE one OF sample IS BEGIN PROCESS ( )
VARIABLE a,b,c : integer range…; BEGIN c := a+b ; END PROCESS;
END ARCHITECTURE one ; 程序3：
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 IS
PORT ( a,b : IN STD_LOGIC ; sel : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END ENTITY mux21 ;
ARCHITECTURE one OF mux21 IS BEGIN PROCESS ( ) BEGIN
IF sel = ?0? THEN c<=a ; ELSE c<=b ; END IF ; END PROCESS;
END ARCHITECTURE one ;
第4章 Quartus II使用方法
习题
4-1
第5章 VHDL状态机