class->ref des->new sub class->silkscreen_top
最后选你准备改变的TEXT,框住要修改的所有TEXT可以批量修改, 注意：
如果修改顶层丝印要先关掉底部丝印层,silkscreen_bottom和display_bottom
--------------------------------------------------------------------
在建封装的时候可以设定
36. Allegro静态铺铜时，当用Shape void Element来手动避让时，有些区域明明很宽但老是进不去以致导致出现孤岛？
答：在用Shape Void Element命令时，选中Shape，右键Parameter，Void Controls->Creat Pin voids，将In-Line改为Individually即可。
37. 重叠元件，如何切换选中它们？
答：选中该最上面元件，按Tab逐层切换选中。
38. 画封装的时候,明明已经在某些层上有定义,如Rout Keepout等，但是调用元件到板上却老是找不到该层？
答：可能有两个原因：1、PCB板上没显示该层；2、画封装的时候，如Top层定义成“Top_Cond”，但PCB上却定义成“TOP”，所以显示不出来。 39. 动态铺铜时，Update to Smooth但还是存在Out of date shapes，什么原因？
答：可能存在一些dummy net 的shapes，可以通过在Report里运行Shape dynamic state来找到这些shapes，又因为dummy net的shapes可能不会就这样显示出来，可以stack-up里boundary那栏打开，用shape select来选中它来删除。
40. Package Geometry 里的Silkscreen画的是封装的外框，Component Geometry里的Silkscreen是器件的编号文本如R1等。
41. Place_Bound_Top
Used to ensure you don’t place components on top of each without getting a DRC. This boundary normally defines the component area which may or may not include pins of surface mount devices. This boundary can also be assigned a component high to be verified at the board level and checked to the Package_Keepout_Top boundaries or any other special component clearances. If this boundary does not exist than it will be
automatically created based on the Assembly_Top outline and the outer extents of the component pins. This boundary can only be defined at the symbol level (.dra).
Dfa_Bound_Top
Used by the Real Time Design for Assembly (DFA) Analysis to check clearances between components driven by a Spreadsheet based matrix of components. This boundary normally or can be different then the
traditional Place_Bound_Top boundary and it may include pins of surface mount devices. If this boundary does not exist than the DFA checks default to using the Place_Bound_Top boundary. This boundary can only be defined at the symbol level (.dra).
Package_Keepout_Top
Used to ensure you don’t violate placement keepout areas or high restricted area in a design. This boundary can only be defined at the board level (.brd) and cannot be added to the symbol level (.dra) unless it is part of a Mechanical Symbol (.bsm)
42. allegro导出库时，no library dependencies选项有什么用？ 答：选中该选项，导出库时会连同焊盘一起导出去。 43. Constraints manager里无法建立pin pair？
答：有可能是虽然已经给电阻、电容等器件建立Espice模型了，但是IC的pin脚IO属性没定义。可以编辑pin脚的属性，找到pinuse项，在里面更改即可。
不错的帖子
http://blog.ednchina.com/szcx1688/37047/Message.aspx
http://hedanwen.blog.163.com/blog/static/7252885201052383847763/