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LIBRARY altera_mf; USE altera_mf.all; ENTITY cyy_sj IS
PORT(address: IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock: IN STD_LOGIC ;
q
: OUT STD_LOGIC_VECTOR (9 DOWNTO 0));
END cyy_sj;
ARCHITECTURE SYN OF cyy_sj IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0); COMPONENT altsyncram
GENERIC (clock_enable_input_a : STRING;
clock_enable_output_a init_file : STRING;
intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode outdata_aclr_a
: STRING; : STRING;
: STRING;
outdata_reg_a : STRING; widthad_a : NATURAL; width_a
: NATURAL;
width_byteena_a : NATURAL);
PORT (clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (9 DOWNTO 0));
END COMPONENT; BEGIN
q <= sub_wire0(9 DOWNTO 0);
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altsyncram_component : altsyncram
GENERIC MAP (clock_enable_input_a => \
clock_enable_output_a => \init_file => \intended_device_family => \lpm_hint => \lpm_type => \numwords_a => 1024, operation_mode => \outdata_aclr_a => \outdata_reg_a => \widthad_a => 10, width_a => 10, width_byteena_a => 1)
PORT MAP (clock0 => clock, address_a => address, q_a => sub_wire0);
END SYN; 仿真结果：
4.6方波产生模块
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该模块输入信号由时钟(clk)和复位信号(reset)构成,当信号发生器选择信号(sel[2..0])为5时,该模块输出端(q [9..0])对外输出。模块振幅随时钟的变化持续变为高电平 或低电平,输出波形参数可以通过程序进行设定。 VHLIBRARY ieee;
USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY cyy_square IS
PORT(address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0));
END cyy_square；
ARCHITECTURE SYN OF cyy_square IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0); COMPONENT altsyncram
GENERIC (clock_enable_input_a : STRING;
clock_enable_output_a init_file : STRING;
intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode outdata_aclr_a
: STRING; : STRING;
: STRING;
outdata_reg_a : STRING; widthad_a : NATURAL; width_a
: NATURAL;
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width_byteena_a : NATURAL);
PORT (clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (9 DOWNTO 0));
END COMPONENT BEGIN
q <= sub_wire0(9 DOWNTO 0); altsyncram_component : altsyncram
GENERIC MAP (clock_enable_input_a => \
clock_enable_output_a => \init_file => \intended_device_family => \lpm_hint => \lpm_type => \numwords_a => 1024, operation_mode => \outdata_aclr_a => \outdata_reg_a => \widthad_a => 10, width_a => 10, width_byteena_a => 1)
PORT MAP (clock0 => clock,
address_a => address, q_a => sub_wire0);
END SYN； 仿真结果：
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4.7锯齿波产生模块
VHDL程序： LIBRARY ieee;
USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY cyy_jc IS
PORT(address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock
: IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0 );
END cyy_jc;
ARCHITECTURE SYN OF cyy_jc IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0); COMPONENT altsyncram
GENERIC (clock_enable_input_a : STRING;
clock_enable_output_a init_file
: STRING;
: STRING;
intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING;