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numwords_a : NATURAL; operation_mode: STRING; outdata_aclr_a: STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a
: NATURAL;
width_byteena_a : NATURAL );
PORT (clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (9 DOWNTO 0));
END COMPONENT; BEGIN
q <= sub_wire0(9 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (clock_enable_input_a => \
clock_enable_output_a => \init_file => \intended_device_family => \lpm_hint => \lpm_type => \numwords_a => 1024, operation_mode => \outdata_aclr_a => \outdata_reg_a => \widthad_a => 10, width_a => 10, width_byteena_a => 1)
PORT MAP (clock0 => clock,
address_a => address,
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q_a => sub_wire0);
END SYN;
4.8输出波形选择模块
VHDL程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY cyy_MUX IS
PORT(Q1,Q2,Q3,Q4:IN STD_LOGIC_VECTOR(9 DOWNTO 0); A1,A0:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END;
ARCHITECTURE ONE OF cyy_MUX IS
SIGNAL A:STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL A2,A3:STD_LOGIC; BEGIN PROCESS(A1) BEGIN
IF A1'EVENT AND A1='0' THEN
IF A2='0' THEN A2<='1'; ELSE A2<='0';
END IF; END IF; END PROCESS; PROCESS(A0) BEGIN
IF A0'EVENT AND A0='0' THEN
IF A3='0' THEN
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A3<='1'; ELSE A3<='0';
END IF; END IF; END PROCESS; A<=A2&A3;
Q<=Q1 WHEN A=\
Q2 WHEN A=\Q3 WHEN A=\ Q4;
END;
5.软硬件调试
5.1软件调试
程序编写完成且准确无误后，将FPGA板接入计算机，安装完成后下载，逻辑分析仪显示下图所示正弦波波形。
三角波、方波、锯齿波的调试过程与正弦波雷同。
5.2硬件调试
将焊接并测试好的外部硬件电路与FPGA连接好，接上电源，调整频率与波
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形控制开关，利用示波器观察输出的波形。
5.2.1正弦波波形
5.2.2三角波波形
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5.2.3方波波形
5.2.4锯齿波波形
硬件调试注意点：
（1）电路板接入电路前，不能直接放在仪器外壳上，因为电路板反面焊点是裸露的，放在仪器上容易出现短路，烧毁电路板。
（2）在将电路板与FPGA接入电路时，要先将实物与FPGA开发板接好，再给