# -- Compiling module stratixiii_lvds_rx
# -- Compiling module stratixiii_lvds_rx_channel # -- Compiling module stratixiii_lvds_rx_dpa # -- Compiling module altlvds_tx
# -- Compiling module stratixv_local_clk_divider # -- Compiling module stratix_tx_outclk # -- Compiling module stratixii_tx_outclk # -- Compiling module flexible_lvds_tx # -- Compiling module dcfifo_dffpipe # -- Compiling module dcfifo_fefifo # -- Compiling module dcfifo_async # -- Compiling module dcfifo_sync
# -- Compiling module dcfifo_low_latency # -- Compiling module dcfifo_mixed_widths # -- Compiling module dcfifo
# -- Compiling module altaccumulate # -- Compiling module altmult_accum # -- Compiling module altmult_add # -- Compiling module altfp_mult # -- Compiling module altsqrt # -- Compiling module altclklock # -- Compiling module altddio_in # -- Compiling module altddio_out # -- Compiling module altddio_bidir # -- Compiling module altdpram # -- Compiling module altsyncram # -- Compiling module alt3pram # -- Compiling module parallel_add # -- Compiling module scfifo
# -- Compiling module altshift_taps # -- Compiling module a_graycounter # -- Compiling module altsquare
# -- Compiling module altera_std_synchronizer
# -- Compiling module altera_std_synchronizer_bundle # -- Compiling module alt_cal
# -- Compiling module alt_cal_mm # -- Compiling module alt_cal_c3gxb # -- Compiling module alt_cal_sv # -- Compiling module alt_aeq_s4 # -- Compiling module alt_eyemon # -- Compiling module alt_dfe # -- Compiling module signal_gen
# -- Compiling module jtag_tap_controller # -- Compiling module dummy_hub
# -- Compiling module sld_virtual_jtag # -- Compiling module sld_signaltap # -- Compiling module altstratixii_oct
# -- Compiling module altparallel_flash_loader # -- Compiling module altserial_flash_loader # -- Compiling module sld_virtual_jtag_basic # -- Compiling module altsource_probe #
# Top level modules: # lcell # altpll # altlvds_rx # altlvds_tx # dcfifo
# altaccumulate # altmult_accum # altmult_add # altfp_mult # altsqrt # altclklock # altddio_bidir # altdpram # alt3pram # parallel_add # scfifo
# altshift_taps # a_graycounter # altsquare
# altera_std_synchronizer_bundle # alt_cal
# alt_cal_mm # alt_cal_c3gxb # alt_cal_sv # alt_aeq_s4 # alt_eyemon # alt_dfe
# sld_virtual_jtag # sld_signaltap # altstratixii_oct
# altparallel_flash_loader # altserial_flash_loader # sld_virtual_jtag_basic # altsource_probe #
# vlib verilog_libs/altera_lnsim_ver
# ** Warning: (vlib-34) Library already exists at \#
# vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver # Modifying modelsim.ini
# vlog -sv -work altera_lnsim_ver {d:/altera/11.1/quartus/eda/sim_lib/altera_lnsim.sv} # Model Technology ModelSim SE vlog 10.1a Compiler 2012.02 Feb 22 2012 # -- Compiling package altera_lnsim_functions
# ** Warning: d:/altera/11.1/quartus/eda/sim_lib/altera_lnsim.sv(1001): (vlog-LRM-2244) Variable 'mega' is implicitly static. You must explicitly declare it as static or automatic. #
# -- Compiling module altera_pll
# -- Importing package altera_lnsim_functions # -- Compiling module altera_stratixv_pll
# -- Compiling package altera_generic_pll_functions
# ** Warning: d:/altera/11.1/quartus/eda/sim_lib/altera_lnsim.sv(4060): (vlog-LRM-2244) Variable 'factor' is implicitly static. You must explicitly declare it as static or automatic. #
# -- Compiling module generic_pll
# -- Importing package altera_generic_pll_functions # -- Compiling module generic_cdr
# -- Compiling module common_28nm_ram_pulse_generator # -- Compiling module common_28nm_ram_register # -- Compiling module common_28nm_ram_block # -- Compiling module generic_m20k # -- Compiling module generic_m10k
# -- Compiling module common_28nm_mlab_cell_pulse_generator # -- Compiling module common_28nm_mlab_cell # -- Compiling module generic_mlab_cell # -- Compiling module generic_mux
# -- Compiling module generic_device_pll # -- Compiling module altera_mult_add
# -- Compiling module ama_signed_extension_function # -- Compiling module ama_dynamic_signed_function # -- Compiling module ama_register_function
# -- Compiling module ama_register_with_ext_function # -- Compiling module ama_data_split_reg_ext_function # -- Compiling module ama_coef_reg_ext_function # -- Compiling module ama_adder_function # -- Compiling module ama_multiplier_function # -- Compiling module ama_preadder_function # -- Compiling module ama_accumulator_function # -- Compiling module ama_systolic_adder_function # -- Compiling module ama_scanchain
#
# Top level modules: # altera_pll # generic_cdr # generic_m20k # generic_m10k # generic_mlab_cell # generic_mux
# generic_device_pll # altera_mult_add #
# vlib verilog_libs/cycloneii_ver
# ** Warning: (vlib-34) Library already exists at \#
# vmap cycloneii_ver ./verilog_libs/cycloneii_ver # Modifying modelsim.ini
# vlog -vlog01compat -work cycloneii_ver {d:/altera/11.1/quartus/eda/sim_lib/cycloneii_atoms.v} # Model Technology ModelSim SE vlog 10.1a Compiler 2012.02 Feb 22 2012 # -- Compiling UDP CYCLONEII_PRIM_DFFE # -- Compiling UDP CYCLONEII_PRIM_DFFEAS
# -- Compiling UDP CYCLONEII_PRIM_DFFEAS_HIGH # -- Compiling module cycloneii_dffe # -- Compiling module cycloneii_mux21 # -- Compiling module cycloneii_mux41 # -- Compiling module cycloneii_and1 # -- Compiling module cycloneii_and16 # -- Compiling module cycloneii_bmux21 # -- Compiling module cycloneii_b17mux21 # -- Compiling module cycloneii_nmux21 # -- Compiling module cycloneii_b5mux21
# -- Compiling module cycloneii_ram_pulse_generator # -- Compiling module cycloneii_ram_register # -- Compiling module cycloneii_ram_block # -- Compiling module cycloneii_jtag # -- Compiling module cycloneii_crcblock # -- Compiling module cycloneii_asmiblock # -- Compiling module cycloneii_m_cntr # -- Compiling module cycloneii_n_cntr # -- Compiling module cycloneii_scale_cntr # -- Compiling module cycloneii_pll_reg # -- Compiling module cycloneii_pll
# -- Compiling module cycloneii_routing_wire # -- Compiling module cycloneii_lcell_ff # -- Compiling module cycloneii_lcell_comb
# -- Compiling module cycloneii_asynch_io # -- Compiling module cycloneii_io
# -- Compiling module cycloneii_clk_delay_ctrl # -- Compiling module cycloneii_clk_delay_cal_ctrl # -- Compiling module cycloneii_ena_reg # -- Compiling module cycloneii_clkctrl
# -- Compiling module cycloneii_mac_data_reg # -- Compiling module cycloneii_mac_sign_reg
# -- Compiling module cycloneii_mac_mult_internal # -- Compiling module cycloneii_mac_mult # -- Compiling module cycloneii_mac_out #
# Top level modules: # cycloneii_and1 # cycloneii_and16 # cycloneii_bmux21 # cycloneii_b17mux21 # cycloneii_nmux21 # cycloneii_b5mux21 # cycloneii_ram_block # cycloneii_jtag # cycloneii_crcblock # cycloneii_asmiblock # cycloneii_pll
# cycloneii_routing_wire # cycloneii_lcell_ff # cycloneii_lcell_comb # cycloneii_io
# cycloneii_clk_delay_ctrl # cycloneii_clk_delay_cal_ctrl # cycloneii_clkctrl # cycloneii_mac_mult # cycloneii_mac_out #
# if {[file exists rtl_work]} { # vdel -lib rtl_work -all # }
# vlib rtl_work
# vmap work rtl_work # Modifying modelsim.ini #
# vlog -vlog01compat -work work +incdir+G:/code/verilog\\ test/20150411_basic_tool/t5 {G:/code/verilog test/20150411_basic_tool/t5/ROM.v}
# Model Technology ModelSim SE vlog 10.1a Compiler 2012.02 Feb 22 2012