XXX大学本科生毕业论文
else
next_state <= st1; end if;
when st2 => if flag = '1' then
if ( a1 or a2 or a3 or a4 or b ) = '1' then next_state <= st2;
else
next_state <= st1; end if; else
next_state <= st2;
end if;
end case; end process;
process ( clk, cur_state ) begin
case cur_state is
when st1 => cnt <= \ flag <= '0';
when st2 => if clk'event and clk = '1' then if cnt = \ cnt <= \ flag <= '1';
else cnt <= cnt + '1';
flag <= '0';
end if; end if;
end case;
end process;
36
XXX大学本科生毕业论文
process ( clk, rst, cur_state ) --状态机输出 begin
if rst = '1' then q <= '0'; else
if clk'event and clk = '1' then
if cur_state = st2 and start1 = ’1’ then
q <= '1';
else
q <= '0';
end if;
end if; end if; end process; end one;
3、光报警模块程序源代码led.vhd library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity led is
Port ( clk : in std_logic; --频率1MHZ的时钟信号 rst : in std_logic; --复位信号 q1 : in std_logic; --报警触发信号 r : out std_logic; --红灯输出 g : out std_logic; --绿灯输出 y : out std_logic); --黄灯输出 end led;
37
XXX大学本科生毕业论文
architecture one of led is type state is ( s0, s1, s2, s3 );
signal per_state, next_state: state; --定义当前状态和下一状态 signal cnt1, cnt2, cnt3: std_logic_vector ( 7 downto 0 ) ; --仿真用此语句 --signal cnt1, cnt2, cnt3: std_logic_vector ( 7 downto 0 ) ; --实际使用此语句 signal flag1, flag2, flag3: std_logic; begin
process ( rst, clk ) --每个时钟上升沿，更新状态 begin
if rst = '1'then --状态机复位
per_state <= s0;
elsif clk'event and clk ='1 'then --状态更新 per_state <= next_state;
end if; end process;
process ( per_state, next_state, q1, flag1, flag2, flag3 ) --状态转移进程 begin
case per_state is
when s0 => if q1 ='1' then next_state <= s1; else
next_state <= s0; end if;
when s1 =>if q1 ='1' then
if flag1 = '1' then next_state <= s2; else
next_state <= s1;
end if;
38
XXX大学本科生毕业论文
else
next_state <= s0;
end if;
when s2 => if q1 ='1' then
if flag2 ='1' then next_state <= s3; else
next_state <= s2;
end if; else
next_state <= s0;
end if;
when s3 => if q1 = '1' then
if flag3 = '1' then next_state <= s1; else
next_state <= s3;
end if; else
next_state <= s0;
end if;
end case; end process;
process ( per_state, clk ) begin
case per_state is
when s0 => cnt1 <= \
flag1 <= '0';
cnt2 <= \
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XXX大学本科生毕业论文
flag2 <= '0';
cnt3 <= \
flag3 <= '0';
when s1 => if clk'event and clk = '1' then
if cnt1 = \ cnt1 <= \ flag1 <= '1';
else
cnt1 <= cnt1 + '1';
flag1 <= '0';
end if; end if;
when s2=>if clk'event and clk = '1' then
if cnt2 = \ cnt2 <= \ flag2 <= '1';
else
cnt2 <= cnt2 + '1';
flag2 <= '0';
end if; end if;
when s3 => if clk'event and clk = '1' then
if cnt3 = \ cnt3 <= \ flag3 <= '1';
else
cnt3 <= cnt3+'1';
flag3 <= '0';
end if; end if;
40
XXX大学 毕业设计（论文）
防盗报警的设计
年 级：xxx级 ■本科 学生学号：xxx
学生姓名：xxx 指导教师：xxx 学生单位：信息工程学院 技术职称：讲师
学生专业：电子信息工程 教师单位：信息工程学院
XXX 大 学 教 务 处
XXX大学本科生毕业论文 I
汽车电子防盗报警系统设计
摘要：随着人民生活水平的不断提高，汽车的普及应用为人们的生活带来了方便，但也给人们提出了一大难题——汽车防盗。本文采用自顶向下的EDA设计方法，用VHDL语言进行基于可编程逻辑器件的汽车电子防盗报警系统软件设计。系统划分为四个模块：启动/解除警戒模块、检测信号模块、光报警模块和声音报警及锁止模块，其中检测信号模块和光报警模块用有限状态机实现。本设计采用Xilinx ISE进行前端设计输入、后端布局布线及配置下载；用Modelsim软件对系统进行功能仿真；用Leonado Spectrum进行综合。系统实现了实时监测非法入侵，及时声光报警、启动/解除警戒和禁止非法使用发动机移动车辆等基本功能。
关键词：自顶向下；有限状态机；VHDL语言；汽车防盗
XXX大学本科生毕业论文 II
The Software Design of Guarding Against Theft and Alarm
System about Automobile
Abstract: With the incessant improvement of the standard of living, the popularization of the car brings much convenience in people's life, but at the same time the use of the car also brings a big problem--guard against theft of cars. In this paper, it adopts top-down design method of EDA and carries through the design of guarding against theft and alarm system about automobile with VHDL language, which bases on Programmable Logic Device (PLD). The system is consist of four modules, including starting and closing alertness module, detecting signal module, alarm of sound and locked module, alarm of light module, detect signal module and alarm of light module were carried out by finite state machine. This design uses Xilinx ISE to carry through foreside inputting design, placing route and configuring download of back-end; Function simulating of the system was carried out by Modelsim; It uses Leonado Spectrum to carry through synthesis. The system carries out some basic functions, there are detecting inbreak in real time, alarming through sound and light in time, starting and closing alertness, forbidding moving car by engine and so on.
Key words: top-down, finite state machine, VHDL language, guard against theft of automobile
XXX大学本科生毕业论文 III
目 录
第1章 绪论 ······················································································································· 1
1.1 课题背景、目的和意义 ····················································································· 1
1.1.1 课题的背景 ······························································································ 1 1.1.2 课题的目的和意义 ·················································································· 4 1.2 论文的主要内容 ································································································· 4 1.3 本章小结 ············································································································· 4 第2章 汽车防盗报警系统整体设计 ················································································· 5
2.1 系统分析与设计 ································································································· 5
2.1.1 设计要求 ·································································································· 5 2.1.2 系统分析 ·································································································· 5 2.2 系统工作原理及模块划分 ················································································· 6 2.3 本章小结 ············································································································· 7 第3章 系统软件设计 ········································································································· 8
3.1 VHDL编程语言 ································································································· 8 3.2 系统模块设计 ····································································································· 8
3.2.1 启动/解除警戒模块设计 ········································································· 8 3.2.2 检测信号模块设计 ·················································································· 9 3.2.3 光报警模块设计 ···················································································· 12 3.2.4 声音报警及锁止模块设计 ···································································· 15 3.3 系统顶层设计 ··································································································· 15 3.4 本章小结 ··········································································································· 16 第4章 系统模块实现 ······································································································· 18
4.1 调试与仿真综合软件介绍 ··············································································· 18 4.2 系统模块实现 ··································································································· 19
4.2.1 启动/解除警戒模块实现 ······································································· 20
XXX大学本科生毕业论文 IV
4.2.2 检测信号模块实现 ················································································ 20 4.2.3 光报警模块实现 ···················································································· 21 4.2.4 声音报警及锁止模块实现 ···································································· 23
4.3 本章小结 ··················································································································· 24 第5章 系统顶层实现 ······································································································· 25
5.1 系统顶层仿真 ····································································································· 25 5.2 系统顶层综合 ····································································································· 26 5.3 系统引脚锁定 ····································································································· 26 5.4系统实现过程及布线后仿真 ·············································································· 27 5.5 使用iMPACT进行下载配置············································································· 28 5.6 本章小结 ············································································································· 30 结论 ····································································································································· 31 致谢 ····································································································································· 32 参考文献 ····························································································································· 33 附录 ····································································································································· 34
XXX大学本科生毕业论文
结 论
本系统是基于可编程逻辑器件的软件设计，根据EDA设计的思路，采用了自顶向下的设计方法进行汽车防盗报警系统的设计。整个系统划分为四个模块：启动/解除警戒模块、检测信号模块、声音报警及锁止模块和光报警模块。启动/解除警戒模块通过led灯显示系统工作状态，启动警戒灯亮，解除警戒灯灭；检测信号模块采用米利型有限状态机实现，实现了实时监测系统的功能；光报警模块采用摩尔型有限状态机实现，实现了红绿黄三个led灯依次轮流闪烁进行光报警的功能，其中每个灯亮两秒；声音报警及锁止模块实现了声音报警，并具有锁住车门，锁止汽车发动机的功能。四个模块通过系统顶层连接起来，实现了汽车防盗报警的功能。程序采用Xilinx ISE进行前端设计输入、后端布局布线及配置下载；用Modelsim软件对系统进行功能仿真，得到了各个模块和整个系统的功能仿真波形图；用Leonado Spectrum进行综合，得到系统综合优化后的寄存器传输级原理图和结构视图。
本设计虽然实现了汽车防盗报警的功能，但是设计中还是有许多需要改进的地方。在声音报警方面，可以设计喇叭发出不同频率的报警声音。在对外部时钟信号的处理上，可以在系统中增加时钟分频模块先对时钟信号进行分频，这样，在计数的时候就可以设置小数值的计数器。整个汽车防盗报警系统的功能比较的简单，在功能方面还有很大改进和扩展空间，比如设置静音防盗功能，自动提示开启防盗等。静音防盗功能即是在系统正常工作状态下，若有非法入侵信号，喇叭不响，但不影响防盗功能；自动提示开启防盗功能就是在汽车停泊后一定的短时间内，系统发出提示音提醒车主开启防盗系统等等。
31
XXX大学本科生毕业论文
致 谢
首先感谢我的毕业设计的导师XXX老师，感谢她的督促和耐心的指导，同时也感谢帮助过我的同学们。在你们的帮助下，我才能更深刻的了解此次设计的任务目的，做出今天的成果。从你们的帮助中，我不仅学到了更多的专业知识，也学到了很多做人的道理。在此，我真心的感谢你们。
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参考文献
[1] 肖军.现代汽车防盗看好智能化的发展方向[J].交通与运输，2006，2：38-39.
[2] 求是科技，张立科.CPLD/FPGA应用开发技术与工程实践[M].北京：人民邮电出版社，2005：
3-21，245-280.
[3] 潘松，黄继业.EDA技术与VHDL[M].北京：清华大学出版社，2005：5-16. [4] 齐洪喜，陆颖.VHDL电路设计使用教程[M].北京：清华大学出版社，2004：10-22. [5] 侯伯亨，顾新.VHDL硬件描述语言与数字电路逻辑设计(修订版)[M].西安：西安电子科技大
学出版社，1999：65-72.
[6] 段有艳.基于Xilinx ISE软件平台用VHDL实现FPGA电路设计[J].昆明冶金高等专科学校学
报，2005，22（3）76-80 .
[7] 王诚，薛小刚，钟信潮.FPGA/CPLD设计工具——Xilinx ISE 5.X使用详解[M].北京：人民
邮电出版社，2003：86-96，121-178.
[8] 吴佳凤，肖安，聂兵.基于VHDL的有限状态机设计方法与实现[J].武汉工业学院学报，2005，
25（1）：12-14.
[9] 张常年.基于VHDL语言的远程拨号智能预警系统[J].计算机应用，2002，22（1）：47-49. [10] 刘桂华，马建国.基于VHDL语言的智能拨号报警器的设计[J].电子技术应用，2001，3：78-80. [11] 张曦，李文元，丁润涛.基于CPLD防盗报警系统设计[J].电子测量技术，2004，3：20-21. [12] 张文英，邹晴，柴燕.基于VHDL语言的数字电路设计[J].中国仪器仪表，2003，3：95-96. [13] 付家才.EDA工程实践技术[M].北京：化学工业出版社，2005：93-132.
[14] Xiong Guohai ，Xiang Xuejun ，Hu Zhaowei .Application of VHDL Language in Control
System[J].The Seventh International Conference on Electronic Measurement and Instruments，2005，7：647-649. [15] Xilinx Inc. ISE Quick Start Tutorial. Xilinx[M].Xilinx，2003：11-41.
[16] Steven Golson. State machine design techniques for Verilog and VHDL[J].Carlisle ，1994：2-22. [17] Douglas L.Perry. VHDL Programming by Example[M].McGraw-Hill，2002：270-295.
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XXX大学本科生毕业论文
附 录
1、启动/解除警戒模块程序源代码on_off.vhd library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity on_off is
Port ( sta : in std_logic; led1 : out std_logic); end on_off;
architecture one of on_off is begin process ( sta ) begin
if sta = '1' then led1 <= '1'; else led1 <= '0'; end if; end process; end one;
2、检测信号模块程序源代码test.vhd library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is
Port ( clk : in std_logic; --频率1MHZ的时钟信号
34
XXX大学本科生毕业论文
rst : in std_logic; --复位信号
a1 : in std_logic; --汽车异常移动信号 a2 : in std_logic; --汽车异常振动信号 a3 : in std_logic; --汽车异常提升信号 a4 : in std_logic; --汽车车身异常倾斜信号 b : in std_logic;
--非法启动发动机信号
start1 : in std_logic; --启动检测系统触发信号 q : out std_logic); --检测结果输出 end test;
architecture one of test is
type states is ( st1, st2 ); --st1:检测状态;st2:报警状态 signal cur_state, next_state: states; --定义当前状态和下一状态 signal flag: std_logic; --标志位
signal cnt: std_logic_vector ( 7 downto 0 ); --定义计数，仿真用此语句 --signal cnt: std_logic_vector ( 22 downto 0 ); --实际用以下语句 begin
process (clk, rst ) --每个时钟上升沿，更新状态 begin
if rst = '1' then --状态机复位
cur_state <= st1;
elsif clk'event and clk = '1' then --状态更新 cur_state <= next_state;
end if; end process;
process ( cur_state, next_state, a1, a2, a3, a4, b, flag ) begin
case cur_state is
when st1 => if ( a1 or a2 or a3 or a4 or b ) = '1' then next_state <= st2;
35
XXX大学本科生毕业论文
图4-2 启动/解除警戒模块的仿真波形图
信号状态和报警状态，还多设置了一个等待状态s0,它通过输入信号led1的值来判断状态机的下一个转移，即是当整个系统启动时，由等待状态进入检测信号状态。由于设置了这一状态，因此在状态机的输出进程中就与输入信号无关了。当时理论上分析认为这样的设计应该是可以实现想要的功能的，可通过分析仿真结果，发觉这样的设计并不能完全的实现模块应有的功能。一开始系统开启，得到的结果是正确的，可开启之后再解除，状态机却仍然在状态s1,s2之间转换，输出结果仍然有效，这样的话，就没有实现该实现的功能。结果不正确，就需要修改源程序，通过多次的修改和调试，最后在程序中用米利型状态机状态机设计，功能仿真结果相符。由于源程序中使用了23位的二进制计数器，计数的值太大，在仿真中耗时太长，因而在程序中把计数器设置为8位的二进制计数器，这样就能比较及时的看到和分析仿真结果，这样的修改不影响模块的功能实现。
仿真前建立的sim.do中，始终信号的设置如下，在下面的语句中-rep 10表示以10ns为时钟周期进行循环设置，成为一个时钟信号。
force clk 0 0,1 5,0 10 -rep 10
通过调试仿真，得出检测信号模块的仿真波形图如图4-3，4-4。仿真完毕，运用 Leonardo Spectrum 综合工具对本模块进行综合。 4.2.3 光报警模块实现
这个模块在调试仿真的过程中出现了不少问题，经过多次修改，才实现了模块要求的功能。在最开始设计的时候，本意也是用状态机来实现，不过在程序中只设置了一个计数器，且把计数器单独放到一个进程里实现，而在状态机进程中就没有设置辅助进程，在状态转移进程里根据计数器的取值范围了确定当前状态和下一状
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图4-3 检测信号模块仿真整体波形图
图4-4 检测信号模块仿真部分波形图
态，从理论上来看这样是可以实现的，但是通过调试仿真，状态机的四个状态并不能按预想的那样正常运转。经过思考和分析，找出了不妥的地方：整个程序并不能
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说是一个状态机，因为计数器进程是单独的进程，并不属于状态机，这样，程序里状态机部分调用的计数器的值就不能使状态机正常的运转。首次调试失败后，进行了重新设计，把整个程序设计成一个摩尔状态机，这次设置了三个计数器和三个标志位，把计数器放在状态机的辅助进程里实现。程序编译成功后，又进行了仿真，虽然这次要比上次的好很多，但是功能还是没有完全的符合要求，当系统开启，解除，再开启警戒的时候，报警灯并不是先从红灯开始报警，而是随机的。这样当然不行，经过检查分析程序，在s1，s2，s3的转移条件中加上了对输入信号q1的值的判断，再进行调试仿真，完全实现了模块要求的功能。由于源程序中使用的是21位的二进制计数器，计数的值太大，仿真耗时太长，因而在程序中把计数器设置为8位的二进制计数器，这样就能比较及时的看到分析仿真结果，这样的修改不影响模块的功能实现。光报警模块的仿真波形图如图4-5，4-6。仿真完毕，通过Leonardo Spectrum 综合工具对本模块进行综合实现。
图4-5 光报警模块仿真整体波形图
4.2.4 声音报警及锁止模块实现
这个模块的程序编写比较简单，在调试仿真的过程中比较顺利，其仿真波形图如图4-7。仿真完毕，通过Leonardo Spectrum 综合工具对本模块进行综合实现。
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图4-6 光报警模块仿真部分波形图
图4-7 声音报警及锁止模块仿真波形图
4.3 本章小结
这一章简单介绍了调试软件Xilinx ISE集成开发环境，仿真软件ModelSim 和综合工具Leonardo Spectrum，对系统模块程序的调试步骤作了简要的说明，重点介绍了在调试过程中遇到的一些问题以及解决的方法，并给出了四个模块独立的仿真波形图。
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第5章 系统顶层实现
5.1 系统顶层仿真
系统的四个模块通过编译，仿真综合完毕后，就开始进行系统顶层的调试。进行系统顶层调试前，需要先把各个模块添加到系统顶层目录下，并需要先一一的对四个模块进行编译，仿真和综合。完成准备工作，就可以开始编译系统顶层。编译的过程没有出现大的问题，但在仿真中却出现了问题，功能仿真结果与所要求实现的功能不一致，主要是没有实现光报警的功能。而各个模块单独调试的时候是完全实现了相应的功能的，可见问题出现在系统顶层的程序编写中。经过仔细的分析和多次调试，找到了问题所在。在顶层程序中，最开始设置的中间信号有问题，原来设置的为q,q1,q2,设置的中间信号与实际需求不相符，而q,q1,q2在模块的设计中已经存在，这样在顶层程序中有可能引起混乱，因而就无法实现所有的功能。之后，对设置的中间信号进行修改，只设置了一个中间信号aa,用它把模块中的q,q1,q2按相应的关系连接起来。再次进行编译仿真，仿真结果符合要求，其功能仿真波形图如图5-1，5-2所示。
图5-1 系统顶层仿真整体波形图
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图5-2 系统顶层仿真部分波形图
5.2 系统顶层综合
系统顶层也使用Mentor Graphics公司 的Leonardo Spectrum综合工具进行综合。双击Synthesis-Leonardo Spectrum开始进行综合，综合的一切信息都在信息显示窗口显示。综合完毕，通过Launch Tools可以查看系统综合的一些情况。Launch Tools下包括三个选项View RTL Schematic, View Technology Schematic, View Critical Path Schematic。View RTL Schematic可以查看系统设计的寄存器传输级原理，它可以帮助理解设计的源代码。View Technology Schematic查看综合优化后的结构视图，视图模块为FPGA/CPLD的硬件原语，帮助理解电路综合结果，分析关键路径。View Critical Path Schematic显示设计的关键路径，关键路径是最影响工作速度或时序约束的的路径。通过View RTL Schematic查看到本系统的寄存器传输级原理图如图5-3所示。
5.3 系统引脚锁定
完成了综合部分，紧接下来就是系统引脚的锁定。引脚的锁定通过约束编辑器 PACE实现，在资源管理窗选中设计的顶层模块，选择User Constraints 下的Assign Package Pins命令，则生成一个UCF文件，此时就启动PACE进行引脚位置锁定。
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图5-3 系统的寄存器传输级原理图
PACE主要由设计浏览窗口（Design Browser Window），设计对象列表窗口（Design Object List Window），器件结构窗口（Device Architecture Window），引脚封装窗口（Package Pins Window）和引脚封装图例窗口(Package Pins Legend Window)等部分组成。PACE约束引脚位置的基本方法有两种：第一种引脚锁定的方法是在Design Object List Window中双击信号的位置属性（Location）选项，直接指定引脚位置。第二种方法是在Design Object List Window中选定需要约束管脚位置的信号，用鼠标拖到引脚封装窗口的相应位置。系统引脚锁定情况如图5-4所示。引脚锁定完成后，保存用户约束文件，退出PACE。
5.4系统实现过程及布线后仿真
系统实现（Implement）就是将综合输出的逻辑网表翻译成所选器件的底层模块与硬件语言，将设计映射到器件结构上，进行布局布线，达到在选定器件上实现设计的目的。实现主要分为三个步骤：翻译（Translate）逻辑网表，映射（Map）到 器件单元和布局布线（Place & Route）。右键点击Implement Design，选择Properties， 可以对实现过Implement Design，实现过程的三个步骤依次进行实现，实现过程的一切信息都在程的三个步骤进行属性设置，本设计中默认软件的属性设置。双击
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图5-4 系统引脚锁定图 信息显示窗口显示。
实现过程完成后，进行布局布线后仿真。将布局布线的时延信息反标到设计网表中，所进行的时序仿真就叫布局布线后仿真，简称布线后仿真。布线后仿真步骤必须进行，以确保设计功能与FPGA实际运行情况相一致。展开当前资源操作窗口的实现项目，双击布局布线项目下的Generate Post-Place & Route Simulation Model命令，产生布局布线后仿真模型。Xilinx 自动产生的仿真模型名为“top_timesim.vhd”。仿真延时信息文件名为“top_timesim.sdf”。后仿真模型文件自动调用SDF延时文件，将延时信息反标到仿真模型中。调用Modelsim进行布线后仿真，仿真结果与原结果一致，如图5-5所示。
5.5 使用iMPACT进行下载配置
iMPACT是ISE集成的配置工具，具有生成PROM格式的下载文件、向FPGA/CPLD/PROM下载配置文件、验证配置数据是否正确等功能。iMPACT支持四种下载模式：边界扫描(Boundary Scan)模式，从串(Slave Serial)模式、SelectMap模式和Desktop配置模式。边界扫描模式标准统一、设备简单，可以通过JTAG口配置FPGA/CPLD/PROM等多种器件，因而用得也最多。本设计也是采用边界扫描 模式。用iMPACT配置FPGA的过程分为两步，第一步是生成一个BIT文件，准备PROM等配置文件；第二步是下载配置文件。这两步操作步骤利用配置向导完成。
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使用iMPACT生成PROM配置文件如图5-6所示。
图5-5 布线后功能仿真波形图
图5-6 使用iMPACT生成PROM配置文件
使用iMPACT下载配置文件，选择配置连接方式Boundary-Scan Mode,接着选择Boundary-Scan连接检测方式Automatically connet to cable and identify Boundary-Scan chain, 完成后iMPACT将自动连接到下载电缆并检测Boundary-Scan
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连接链，显示边界扫描链的结构，同时提示将为边界扫描链中的器件配置文件。完成配制文件指定后，用鼠标选中器件，单击鼠标右键弹出命令菜单，选中Program命令，设置编程属性，确定后对PROM进行编程。
5.6 本章小结
本章对系统设计的整个流程进行了总体介绍，对系统顶层的调试仿真过程作了
详细的说明，通过仿真得到了系统的功能仿真波形图。文中把整个设计进行了综合优化，得到系统寄存器传输原理图和结构视图。系统后端的布局布线、布线后仿真以及下载配置运用Xilinx ISE实现。文中对系统后端实现也做了详细的说明，并给出了相应的一些图形。
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end case; end process;
process ( clk, rst, per_state ) --状态输出进程 begin
if rst = 1' then
r <= '0'; g <= '0'; y <= '0'; else
if clk'event and clk = '1' then if per_state = s0 then
r <= '0'; g <= '0'; y <= '0'; else
if per_state = s1 then r <= '1';g <= '0'; y <= '0'; else
if per_state = s2 then r <= '0'; g <='1' ;y <= '0'; else
if per_state = s3 then
r <= '0'; g <= '0'; y <= '1'; else r <= '0'; g <= '0'; y <= '0'; end if; end if; end if; end if; end if; end if; end process; end one;
4、声音报警及锁止模块程序源代码sound.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sound is
Port ( start1: in std_logic; b1 : in std_logic; q2 : in std_logic;
led_b : out std_logic; led_door : out std_logic; alarm : out std_logic); end sound;
architecture one of sound is begin
processs ( b1, q2, start1 ) begin
if start1 = '1' then if b1 = '1' then led_b <= '1'; led_door <= '1'; alarm <= '1'; else
if q2 = '1' then led_b <= '0'; led_door <= '1';
alarm <= '1';
else led_b <= '0';
led_door <= '0';
--非法启动发动机信号--非法信号
--锁止发动机输出 --锁止车门输出 --声音报警
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alarm <= '0';
end if; end if; else
led_b <= '0';
led_door <= '0'; alarm <= '0';
end if; end process; end one;
5、系统顶层程序源代码top.vhd library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is
Port ( clk : in std_logic; rst : in std_logic; a1 : in std_logic; a2 : in std_logic; a3 : in std_logic; a4 : in std_logic; b : in std_logic; start : in std_logic; led1 : out std_logic; r : out std_logic; g : out std_logic; y : out std_logic; led_door : out std_logic;
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led_b : out std_logic; alarm : out std_logic ); end top;
architecture one of top is COMPONENT on_off Port ( sta : in std_logic; led1 : out std_logic); end COMPONENT;
COMPONENT test
Port ( clk : in std_logic; --频率1MHZ的时钟信号 rst : in std_logic; --复位信号
a1 : in std_logic; --汽车异常移动信号 a2 : in std_logic; --汽车异常振动信号 a3 : in std_logic; --汽车异常提升信号 a4 : in std_logic; --汽车车身异常倾斜信号 b : in std_logic;
--非法启动发动机信号
start1 : in std_logic; --启动检测系统触发信号 q : out std_logic ); --检测结果输出 end COMPONENT;
COMPONENT led
Port ( clk : in std_logic; --频率1MHZ的时钟信号 rst : in std_logic; --复位信号 q1 : in std_logic;
--报警触发信号
r : out std_logic; --红灯输出 g : out std_logic;
--绿灯输出
y : out std_logic ); --黄灯输出 end COMPONENT;
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COMPONENT sound
Port ( start1: in std_logic; b1 : in std_logic; q2 : in std_logic;
--非法启动发动机信号 --非法信号
led_b : out std_logic; --锁止发动机输出 led_door : out std_logic; alarm : out std_logic); end COMPONENT;
signal aa: std_logic; begin u1: on_off
PORT MAP ( sta => start, led1 => led1); u2: test
PORT MAP (a1 => a1, a2 => a2, a3 => a3, a4 => a4, b => b, clk => clk, rst => rst, start1 => start,
q => aa );
u3: led
PORT MAP( clk => clk, rst => rst,
q1 => aa,
--锁止车门输出 --声音报警
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