电子设计自动化技术实训 CSH
input:in std_logic; reset:in std_logic;
sel:out std_logic_vector( 3 downto 0); show:out std_logic_vector(6 downto 0); decimal:out std_logic_vector(2 downto 0)); end total;
architecture content of total is signal cp_1,cp_2,cp_3:std_logic; signal reset_1:std_logic;
signal overflow_1,low_1:std_logic;
signal play0_1,play1_1,play2_1,play3_1:integer range 0 to 9; signal overlatch_1,lowlatch_1:std_logic;
signal p0latch_1,p1latch_1,p2latch_1:integer range 0 to 9; signal decimal_1:std_logic_vector(2 downto 0); component dividefre4 is port(cp_20m:in std_logic; cp1:out std_logic; cp2:out std_logic; cp3:out std_logic); end component; component debounce is port(key:in std_logic; cp:in std_logic; imp:out std_logic); end component; component fretest is
port(enable,cp3,input,reset:in std_logic; overflow,low:out integer range 0 to 9; decimal:out std_logic_vector(2 downto 0) );
end component; component frelatch is port( reset:in std_logic; cp3:in std_logic; overflow:in std_logic; low:in std_logic;
play0,play1,play2,play3:in integer range 0 to 9; decimal:in std_logic_vector(2 downto 0); overlatch:out std_logic; lowlatch:out std_logic;
21
电子设计自动化技术实训 CSH
p0latch,p1latch,p2latch,p3latch:out integer range 0 to 9; delatch:out std_logic_vector(2 downto 0) ); end component; component display is port(cp1:in std_logic; low:in std_logic; overflow:in std_logic;
p0,p1,p2,p3:in integer range 0 to 9; show:out std_logic_vector(6 downto 0); sel:out std_logic_vector(3 downto 0) );
end component; begin
u1:dividefre4 port map(cp_20m,cp_1,cp_2,cp_3); u2:debounce port map(reset,cp_2,reset_1); u3:fretest 1); u4:frelatch
1,lowlatch_1,p0latch_1,platch_1,p2latch_1p3latch_1decimal); u5:display
map(cp_1,lowlatch_1,overlatch_1,p0latch_1,p1latch_1,p2latch_1,p3latch_1,show,sel); end content; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity debounce is port(key,cp:in std_logic; imp:out std_logic); end debounce;
architecture base of debounce is signal q1,q2:std_logic; begin
process(cp) begin
if cp'event and cp='1'then q2<=q1;
22
port
map(enable,cp_3,input,reset_1,overflow_1,low_1,play0_1,play1_1,play2_1,play3_1,decimal_
port
map(reset_1,cp_3,,overflow_1,low_1,play0_1,play1_1,play2_1,play3_1,decimal_1,overlatch_
port
电子设计自动化技术实训 CSH
q1<=key; end if; end process; imp<=q1 and not q2; end base; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity display is port(cp1:in std_logic; low:in std_logic; overflow:in std_logic;
p0,p1,p2,p3:in integer range 0 to 9; show:out std_logic_vector(6 downto 0); sel:out std_logic_vector(3 downto 0) ); end display;
architecture behavior of display is signal count:integer range 0 to 3;
signal sel_1:std_logic_vector(3 downto 0); begin
provess(cp1) begin
if(cp1'event and cp1='1')then if count=3 then count<=0; else
count<=count+1; end if; end if; end process; precss(count) begin case count is
when0=>sel_1<=\ when1=>sel_1<=\ when2=>sel_1<=\ when3=>sel_1<=\end case; end process;
process(low,overflow)
23
电子设计自动化技术实训 CSH
begin
if(low='1')then show<=\ elsif(overflow='1')then show<=\ elsif(sel_1(0)='0')fthen case p0 is
when0=>show<=\ when1=>show<=\ when2=>show<=\ when3=>show<=\ when4=>show<=\ when5=>show<=\ when6=>show<=\ when7=>show<=\ when8=>show<=\ when9=>show<=\end case;
elsif(sel_1(2)='0')then case p2 is
when0=>show<=\ when1=>show<=\ when2=>show<=\ when3=>show<=\ when4=>show<=\ when5=>show<=\ when6=>show<=\ when7=>show<=\ when8=>show<=\ when9=>show<=\end case;
elsif(sel_1(3)='0')then case p3 is
when0=>show<=\ when1=>show<=\ when2=>show<=\ when3=>show<=\ when4=>show<=\ when5=>show<=\ when6=>show<=\
24
电子设计自动化技术实训 CSH
when7=>show<=\ when8=>show<=\ when9=>show<=\ end if; end process; sel<=sel_1; end behacior; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity dividefre4 is port(cp_20m:in std_logic; cp1:out std_logic; cp2:out std_logic; cp3:out std_logic; end dividefre4;
architecture behavior of dividefre4 is signal tout:integer range 0 to 50000; signal tout1:integer range 0 to 7; signal tout2:integer range 0 to 39; signal cp_1:std_logic; signal cp_2:std_logic; signal cp_3:std_logic; signal cp:std_logic; begin
process(cp_20m) begin
if(cp_20m'event and cp_20m='1')then if tout=49999 then tout<=0; else tout<=tout+1; end if;
if tout=24999 then cp<=0'; else cp<='1'; end if; end if; end process; process(cp) begin
25