电子设计自动化技术实训 CSH
if(cp'event and cp='1')then cp_1<=not cp_1; end if; end process; process(cp_1) begin
if(cp_1'event and cp_1='1') then if tout1=7 then tout1<=0; else tout1<=tout1+1; end if; if tout1=3 then cp_2<='1';
elsif tout1=7 then cp_2<='0'; end if;
if tout2=39 then tout2<=0; else tout2<=tout2+1; end if;
if tout2=39 then cp_3<='1';
elsif tout2=19 then cp_3<='0'; end if; end if; end process;
cp1<=cp_1;cp2<=cp_2;cp3<=cp_3; end behavior; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity frelatch is port( reset:in std_logic; cp3:in std_logic; overflow:in std_logic; low:in std_logic;
play0,play1,play2,play3:in integer range 0 to 9; decimal:in std_logic_vector(2 downto 0); overlatch:out std_logic; lowlatch:out std_logic;
p0latch,p1latch,p2latch,p3latch:out integer range 0 to 9; delatch:out std_logic_vector(2 downto 0) );
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电子设计自动化技术实训 CSH
end frelatch;
architecture behavior of frelatch is begin
process(cp3,reset) begin
if reset='1'then
overlatch<='0';lowlatch<='0';p0latch<=0;p1latch<=0;p2latch<=0;p3latch<=0; delatch<=decimal;
elsif cp3'event and cp3='0'then overlatch<=overflow; lowlatch<=low;
p0latch<=play0;p1latch<=play1;p2latch<=play2;p3latch<=play3; delatch<=decimal; end if; end process; end process; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity fretest is
port(enable:in std_logic; cp3:in std_logic; input:in std_logic; reset:in std_logic; overflow:in std_logic; low:in std_logic;
play0,play1,play2,play3:out integer range 0 to 9; decimal:out std_llogic_vector(2 downto 0)); end fretest;
architecture behavior of fretest is
signal r0_1,r1_1,r2_1,r3_1,r4_1,r5_1:integer range 0 to 9; begin
process(input,enable,reset) begin
if enable='0' then null;
elsif(input'event and input='1') then if reset='1'then
overflow<='0';r0_1<='0';r1_1<='0';r2_1<='0';r3_1<='0';r4_1<='0';r5_1<='0'; elsif cp3='0' then
overflow<='0';r0_1<='0';r1_1<='0';r2_1<='0';r3_1<='0';r4_1<='0';r5_1<='0';
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电子设计自动化技术实训 CSH
else
r0_1=r0_1+1;
if r0_1=9 then r1_1<=r1_1+1;r0_1<=0; if r1_1=9 then r2_1<=r2_1+1;r1_1<=0; if r2_1=9 then r3_1<=r3_1+1;r2_1<=0; if r3_1=9 then r4_1<=r4_1+1;r3_1<=0; if r4_1=9 then r5_1<=r5_1+1;r4_1<=0; if r5_1=9 then r5_1<=0;overflow<='1'; end if; end if; end if; end if; end if;
if (r5_1=0 and r4_1+0 and r3_1=0) then low<='1'; else low<='0'; end if; end if; end if; end process; process(r5_1,r4_1) begin
if r5_1=0 and r4_1=0 then
play0<=r0_1;play1<=r1_1;play2<=r2_1;play3<=r3_1; decimal<=\
elsif r5_1=0 and r4_1>0 then
play0<=r1_1;play1<=r2_1;play2<=r3_1;play3<=r4_1; decimal<=\else
paly0<=r2_1;play1<=r3_1;play3<=r4_1;play3<=r5_1; decimal<=\ end if; end process; end behavior;
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五、 程序说明
1. 此程序由1个上层模块将5个下层模块连接在一起而组成，5个下层模块分别是分
频模块、防抖模块、计数模块、锁存器模块和显示模块。
2. 此程序将时钟分到5HZ ，形成一个固定的0.2S的闸门时间，被测信号通过0.1S的
电子设计自动化技术实训 CSH 29
闸门进入计数器进行计数，而在0.1S的低电平内不计数，将计数器清零，以便下一次计数。
3. 为满足题意，被测信号为几十千赫兹（KHZ）时，显示##.##KHZ；
被测信号为几百千赫兹（KHZ）时，显示###.##KHZ； 被测信号为几千千赫兹（KHZ）时，显示####.##KHZ。
4.采用时分复用的方法控制4个数码管的显示。