uart接收器功能仿真结果
Uart接收器时序仿真结果
Uart接收器编译结果
由ｑｕａｒｔｕｓ功能提供的ＦＩＦＯ
Quartus下megawizard工具提供的FIFO
设置一路时钟输入，wrreq和rdreq分别控制写入和读出操作 提供empty，full工作状态输出 Data{7~0}输入并行数据 Q{7~0}输出并行数据 深度和宽度为8
-- megafunction wizard: %FIFO% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: scfifo
-- ============================================================ -- File Name: Fifo.vhd -- Megafunction Name(s): -- scfifo --
-- Simulation Library Files(s): -- altera_mf
-- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf; USE altera_mf.all;
ENTITY Fifo IS PORT ( clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); rdreq : IN STD_LOGIC ; wrreq : IN STD_LOGIC ; empty : OUT STD_LOGIC ; full : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END Fifo;
ARCHITECTURE SYN OF fifo IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL sub_wire2 : STD_LOGIC ; COMPONENT scfifo GENERIC ( add_ram_output_register : STRING;
intended_device_family : STRING; lpm_numwords : NATURAL; lpm_showahead : STRING; lpm_type : STRING; lpm_width : NATURAL; lpm_widthu : NATURAL; overflow_checking : STRING; underflow_checking : STRING; use_eab : STRING ); PORT ( rdreq : IN STD_LOGIC ; empty : OUT STD_LOGIC ; clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); wrreq : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); full : OUT STD_LOGIC ); END COMPONENT;
BEGIN empty <= sub_wire0; q <= sub_wire1(7 DOWNTO 0); full <= sub_wire2; scfifo_component : scfifo GENERIC MAP ( add_ram_output_register => \ intended_device_family => \ lpm_numwords => 8, lpm_showahead => \ lpm_type => \ lpm_width => 8, lpm_widthu => 3, overflow_checking => \ underflow_checking => \ use_eab => \ ) PORT MAP ( rdreq =>rdreq, clock => clock, wrreq =>wrreq, data => data,
empty => sub_wire0, q => sub_wire1, full => sub_wire2 );
END SYN;
-- ============================================================ -- CNX file retrieval info
-- ============================================================ -- Retrieval info: PRIVATE: AlmostEmpty NUMERIC \-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC \-- Retrieval info: PRIVATE: AlmostFull NUMERIC \-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC \
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC \-- Retrieval info: PRIVATE: Clock NUMERIC \-- Retrieval info: PRIVATE: Depth NUMERIC \-- Retrieval info: PRIVATE: Empty NUMERIC \-- Retrieval info: PRIVATE: Full NUMERIC \
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING \-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC \-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC \
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC \-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC \-- Retrieval info: PRIVATE: Optimize NUMERIC \
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC \
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING \-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC \-- Retrieval info: PRIVATE: UsedW NUMERIC \-- Retrieval info: PRIVATE: Width NUMERIC \-- Retrieval info: PRIVATE: dc_aclr NUMERIC \-- Retrieval info: PRIVATE: diff_widths NUMERIC \-- Retrieval info: PRIVATE: msb_usedw NUMERIC \-- Retrieval info: PRIVATE: output_width NUMERIC \-- Retrieval info: PRIVATE: rsEmpty NUMERIC \-- Retrieval info: PRIVATE: rsFull NUMERIC \-- Retrieval info: PRIVATE: rsUsedW NUMERIC \-- Retrieval info: PRIVATE: sc_aclr NUMERIC \-- Retrieval info: PRIVATE: sc_sclr NUMERIC \-- Retrieval info: PRIVATE: wsEmpty NUMERIC \-- Retrieval info: PRIVATE: wsFull NUMERIC \-- Retrieval info: PRIVATE: wsUsedW NUMERIC \