基于VHDL的uart设计(3)

-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING \-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING \-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC \-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING \-- Retrieval info: CONSTANT: LPM_TYPE STRING \-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC \-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC \

-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING \-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING \-- Retrieval info: CONSTANT: USE_EAB STRING \

-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] -- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] -- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0

-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0

-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0

-- Retrieval info: LIBRARY: altera_mfaltera_mf.altera_mf_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL Fifo.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL Fifo.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL Fifo.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL Fifo.bsf FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL Fifo_inst.vhd FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL Fifo_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL Fifo_wave*.jpg FALSE -- Retrieval info: LIB_FILE: altera_mf

ＦＩＦＯ的编译结果

ＦＩＦＯ的功能仿真结果

ＦＩＦＯ的时序仿真结果

ｕａｒｔ发射器

LIBRARY ieee;

USE ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY transmit IS PORT( clkt : IN STD_LOGIC; 时钟输入 reset : IN STD_LOGIC; 复位 lock : IN STD_LOGIC; 锁存 din : IN STD_LOGIC_VECTOR(7 downto 0); 并行输入 trans : OUT STD_LOGIC; 串行输出 trans_end : OUT STD_LOGIC ); 输出状态 END transmit;

ARCHITECTURE behavioral OF transmit IS BEGIN

pro:process(clkt,reset,lock)

variable number:STD_LOGIC_VECTOR(3 downto 0); variable count:STD_LOGIC_VECTOR(3 downto 0); variable buf:STD_LOGIC_VECTOR(7 downto 0); begin

if reset='1' then 复位操作 number:=\

trans_end<='1';

trans<='1';

count:=\ elsifrising_edge(clkt)then

if (lock='1') and (number<\

if number=\ then 接受并行数据并锁存 if count<\

count:=count+1; else

count:=\ trans_end<='0';

trans<='1';

number:=number+1; buf:=din;

end if;

elsif number = \ 输出起始位 if count<\ count:=count+1; else

count:=\ trans_end<='0';

trans<='0';

number:=number+1; end if;

elsif number>=\ if count<\ count:=count+1; else

count:=\

number:=number+1; trans_end<='0';

trans <= buf(7) ;

buf := buf(6 downto 0)&'0';

end if;

elsif number = \ 输出结束位

if count<\

count:=count+1; else

count:=\trans_end<='0';

trans<= '1' ;

number:=number+1;

输出数据位 end if;

elsif number = \ then if count<\ count:=count+1; else

count:=\trans_end<='1';

trans<= '1' ; number:=number+1; end if; end if;

elsif lock='0' then count:=\ trans_end<='1';

trans<='1';

number:=\ end if; end if;

end process; end behavioral;

ｕａｒｔ发射器编译结果