FIR低通数字滤波器的设计要点(4)

六、参考文献

·[1]朱铭锆,赵勇,甘泉.DSP应用系统设计[M].北京:电子工业出版社,2002. ·[2]程佩青.数字信号处理教程[M].第2版.北京:清华大学出版社,2002. ·[3]楼顺天,李博菡.基于MATLAB的系统分析与设计——信号处理[M].北京:西 安电子科技大学出版社,1998.

·[4]胡广书.数字信号处理——理论、算法与实现[M].北京:清华大学出版 社,1997.

·[5]伍小芹,吴秋丽.FIR数字滤波器在DSP上的实现[J].现代电子技 术,2007(1):85-87.

·[6]朱铭锆,赵勇,甘泉,等.DSP应用系统设计[M].北京:电子工业出版社,2002. ·[8]程佩青.数字信号处理教程[M].2版.北京:清华大学出版社,2002.

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七、附录

实验清单： library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_signed.all;

library dspbuilder;

use dspbuilder.dspbuilderblock.all;

library lpm;

use lpm.lpm_components.all;

Entity Subsystem2 is Port( clock : in std_logic; sclr : in std_logic:='0'; hn1 : in std_logic_vector(11 downto 0); hn2 : in std_logic_vector(11 downto 0); hn3 : in std_logic_vector(11 downto 0); hn4 : in std_logic_vector(11 downto 0); xin : in std_logic_vector(11 downto 0); xn4 : out std_logic_vector(11 downto 0); yn : out std_logic_vector(19 downto 0) );

end Subsystem2;

architecture aDspBuilder of Subsystem2 is

signal SAynO : std_logic_vector(19 downto 0); signal A0W : std_logic_vector(11 downto 0); signal A1W : std_logic_vector(11 downto 0); signal A2W : std_logic_vector(11 downto 0); signal A3W : std_logic_vector(11 downto 0); signal A4W : std_logic_vector(11 downto 0); signal A5W : std_logic_vector(11 downto 0); signal A6W : std_logic_vector(11 downto 0); signal A7W : std_logic_vector(11 downto 0); signal A8W : std_logic_vector(11 downto 0); signal A9W : std_logic_vector(23 downto 0); signal A10W : std_logic_vector(23 downto 0); signal A11W : std_logic_vector(23 downto 0);

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signal A12W : std_logic_vector(23 downto 0); signal A13W : std_logic_vector(25 downto 0); signal p15A0L0Add : std_logic_vector(23 downto 0); signal p15B0L0Add : std_logic_vector(23 downto 0); signal p15A1L0Add : std_logic_vector(23 downto 0); signal p15B1L0Add : std_logic_vector(23 downto 0); signal p15A0L1Add : std_logic_vector(24 downto 0); signal p15B0L1Add : std_logic_vector(24 downto 0);

Begin

assert (1<0) report altversion severity Note;

-- Output - I/O assignment from Simulink Block \xn4 <= A8W; yn <= SAynO;

-- Input - I/O assignment from Simulink Block \A0W <= hn1;

-- Input - I/O assignment from Simulink Block \A1W <= hn2;

-- Input - I/O assignment from Simulink Block \A2W <= hn3;

-- Input - I/O assignment from Simulink Block \A3W <= hn4;

-- Input - I/O assignment from Simulink Block \A4W <= xin;

-- Sum Operator - Simulink Block \p15A0L0Add <= A9W; p15B0L0Add <= A10W; p15A1L0Add <= A11W; p15B1L0Add <= A12W;

-- Output - I/O assignment from Simulink Block \yni : SBF generic map(

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width_inl=>26, width_inr=>0, width_outl=>20, width_outr=>0,

lpm_signed=>BusIsSigned, round=>0, satur=>0) port map ( xin=>A13W, yout=>SAynO);

-- Delay Element - Simulink Block \Delayi : SDelay generic map ( LPM_WIDTH => 12, LPM_DELAY => 1, SequenceLength => 1, SequenceValue => 1) port map (dataa => A4W, clock => clock, ena => '1', sclr => sclr, result => A5W);

-- Delay Element - Simulink Block \Delay1i : SDelay generic map ( LPM_WIDTH => 12, LPM_DELAY => 1, SequenceLength => 1, SequenceValue => 1) port map (dataa => A5W, clock => clock, ena => '1', sclr => sclr, result => A6W);

-- Delay Element - Simulink Block \Delay2i : SDelay generic map ( LPM_WIDTH => 12, LPM_DELAY => 1, SequenceLength => 1, SequenceValue => 1)

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port map (dataa => A6W, clock => clock, ena => '1', sclr => sclr, result => A7W);

-- Delay Element - Simulink Block \Delay3i : SDelay generic map ( LPM_WIDTH => 12, LPM_DELAY => 1, SequenceLength => 1, SequenceValue => 1) port map (dataa => A7W, clock => clock, ena => '1', sclr => sclr, result => A8W);

-- Product Operator - Simulink Block \Producti : AltiMult generic map ( LPM_WIDTHA => 12, LPM_WIDTHB => 12, PIPELINE => 2, one_input => 0, lpm => 0, lpm_hint => \cst_val => \SequenceLength => 1, SequenceValue => 1, dspb_widthr => 24) port map ( DATAA => A5W, DATAB => A0W, clock => clock, ena => '1', sclr => sclr, result => A9W);

-- Product Operator - Simulink Block \Product1i : AltiMult generic map ( LPM_WIDTHA => 12,

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