FIR低通数字滤波器的设计要点(5)

LPM_WIDTHB => 12, PIPELINE => 2, one_input => 0, lpm => 0, lpm_hint => \cst_val => \SequenceLength => 1, SequenceValue => 1, dspb_widthr => 24) port map ( DATAA => A6W, DATAB => A1W, clock => clock, ena => '1', sclr => sclr, result => A10W);

-- Product Operator - Simulink Block \Product2i : AltiMult generic map ( LPM_WIDTHA => 12, LPM_WIDTHB => 12, PIPELINE => 2, one_input => 0, lpm => 0, lpm_hint => \cst_val => \SequenceLength => 1, SequenceValue => 1, dspb_widthr => 24) port map ( DATAA => A7W, DATAB => A2W, clock => clock, ena => '1', sclr => sclr, result => A11W);

-- Product Operator - Simulink Block \Product3i : AltiMult generic map ( LPM_WIDTHA => 12, LPM_WIDTHB => 12, PIPELINE => 2,

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one_input => 0, lpm => 0, lpm_hint => \cst_val => \SequenceLength => 1, SequenceValue => 1, dspb_widthr => 24) port map ( DATAA => A8W, DATAB => A3W, clock => clock, ena => '1', sclr => sclr, result => A12W);

-- Sum Operator - Simulink Block %u15_L0_Inst0 : SAdderSub generic map ( LPM_WIDTH => 24, PIPELINE => 1, SequenceLength => 1, SequenceValue => 1, AddSubVal => AddAdd) port map ( dataa => p15A0L0Add, datab => p15B0L0Add, clock => clock, ena => '1', sclr => sclr, result => p15A0L1Add);

u15_L0_Inst1 : SAdderSub generic map ( LPM_WIDTH => 24, PIPELINE => 1, SequenceLength => 1, SequenceValue => 1, AddSubVal => AddAdd) port map ( dataa => p15A1L0Add, datab => p15B1L0Add, clock => clock, ena => '1', sclr => sclr, result => p15B0L1Add);

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u15_L1_Inst0 : SAdderSub generic map ( LPM_WIDTH => 25, PIPELINE => 1, SequenceLength => 1, SequenceValue => 1, AddSubVal => AddAdd) port map ( dataa => p15A0L1Add, datab => p15B0L1Add, clock => clock, ena => '1', sclr => sclr, result => A13W);

end architecture aDspBuilder;

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