ppoint_ten_C := ppoint_ten_C - 1;
else
ppoint_one_C := ppoint_one_C - 1;
end if;
end if;
if (input(3) = '1') then
if (ppoint_one_D = \
ppoint_one_D := \
ppoint_ten_D := ppoint_ten_D - 1;
else
ppoint_one_D := ppoint_one_D - 1;
end if;
end if;--input
end if;
end if;
end if;
point_one_A <= ppoint_one_A; point_ten_A <= ppoint_ten_A;
point_one_B <= ppoint_one_B; point_ten_B <= ppoint_ten_B;
point_one_C <= ppoint_one_C; point_ten_C <= ppoint_ten_C;
point_one_D <= ppoint_one_D; point_ten_D <= ppoint_ten_D;
end process;
end Behavioral;
防抖模块：
entity shaking is
Port ( clk500 : in STD_LOGIC; input : in STD_LOGIC; output : out STD_LOGIC); end shaking;
architecture Behavioral of shaking is signal flag : STD_LOGIC := '0'; begin
process(clk500, input) is variable count : integer := 0; begin
if(clk500'event and clk500 = '1') then
if (input = '1' and count = 0) then—有输入，将输入延展
count := count + 1; flag <= '1';
elsif (flag = '1') then
if (count <500) then--500
count := count + 1;
else
count := 0; flag <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
output <= flag;
用于判断是否答题超时的计时模块(Timer)
entity timer is
Port ( clk1 : in STD_LOGIC; --1hz
violationflag : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (3 downto 0); reset : in STD_LOGIC; clr : in STD_LOGIC;
resetforpoints : in STD_LOGIC;
timeout : out STD_LOGIC); end timer;
architecture Behavioral of timer is signal en : STD_LOGIC; begin
en <= reset and clr and resetforpoints; process (clk1, en, violationflag, input) is variable count : integer := 0; begin
if (en = '0') then
count := 0; timeout <= '0';
else
if (input /= \正常答题中
if (clk1'event and clk1 = '1') then
if (count < 50) then—50s
count := count + 1;
elsif (count < 55) then—超时，鸣响直至55s
count := count + 1; timeout <= '1';--超时
else
timeout <= '0';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
用于提示犯规的计时模块(Timer3)：
entity timer3 is
Port ( clk1 : in STD_LOGIC; --1hz
violationflag : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (3 downto 0); reset : in STD_LOGIC; clr : in STD_LOGIC;
resetforpoints : in STD_LOGIC;
timeout : out STD_LOGIC); end timer3;
architecture Behavioral of timer3 is signal en : STD_LOGIC; begin
en <= not(reset) and clr and resetforpoints;
process (clk1, en, violationflag, input) is variable count : integer := 0; begin
if (en = '0') then
count := 0; timeout <= '0';
else
if (input /= \犯规
if (clk1'event and clk1 = '1') then
if (count < 2) then
count := count + 1; timeout <= '1';--提示犯规
else—清零
timeout <= '0';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
用于提示有人抢答成功的计时模块(Timer1)：
entity timer1 is
Port ( clk1 : in STD_LOGIC; --1hz
violationflag : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (3 downto 0);