复杂数字电路设计实验报告_数字抢答器(4)

2019-01-27 21:16

reset : in STD_LOGIC; clr : in STD_LOGIC;

resetforpoints : in STD_LOGIC;

timeout : out STD_LOGIC); end timer1;

architecture Behavioral of timer1 is signal en : STD_LOGIC; begin

en <= reset and clr and resetforpoints; process (clk1, en, violationflag, input) is variable count : integer := 0; begin

if (en = '0') then

count := 0; timeout <= '0';

else

if (input /= \—抢答成功

if (clk1'event and clk1 = '1') then

if (count < 2) then

count := count + 1; timeout <= '1';--提示

else

timeout <= '0';

end if;

end if;

end if;

end if;

end process; end Behavioral;

用于产生清零信号的计时模块(Timer2):

entity timer2 is

Port ( clk500 : in STD_LOGIC; --500hz

clr_in : in STD_LOGIC;

clr_out : out STD_LOGIC); end timer2;

architecture Behavioral of timer2 is signal flag : STD_LOGIC := '1'; begin

process (clk500, clr_in) is variable count : integer := 0; begin

if (clk500'event and clk500 = '1') then

if (clr_in = '1') then

count := count + 1;

end if;

if(count /= 0) then

if (count >= 100 and count < 200) then--产生清零信号,滞后100,100

的宽度

flag <= '0'; count := count + 1;

elsif (count >= 200) then--200

flag <= '1'; count := 0;

else

count := count + 1;

end if;

end if;

end if;

end process;

clr_out <= flag;

end Behavioral;

LCD模块:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lcd is

Port ( LCD_Clk : in STD_LOGIC; reset : in STD_LOGIC;

point_ten_A,

point_ten_B,

point_ten_C,

STD_LOGIC_VECTOR (7 downto 0); point_one_A,

point_one_B,

point_one_C,

STD_LOGIC_VECTOR (7 downto 0); LCD_RS : out STD_LOGIC; LCD_RW : out STD_LOGIC; LCD_EN : out STD_LOGIC;

data : out STD_LOGIC_VECTOR(3 downto 0));

end lcd;

architecture Behavioral of lcd is

point_ten_D

point_one_D

:

in

in

:

type iState is(

Write_instr, Write_DataUp4, Write_DataDown4, Set_AddrUp, Set_AddrDown, Ret_HomeUp, Ret_HomeDown );

signal state:iState; signal cnt_clk:std_logic;

signal cnt:integer range 0 to 15:=0; begin

LCD_RW <= '0'; LCD_EN <= LCD_Clk; process(LCD_Clk,reset) begin

if(reset='1')then

state <= Write_instr;

LCD_RS <= '0'; cnt<=0;

elsif(rising_edge(LCD_CLk))then case state is

--写命令字到LCD控制器,初始化液晶,并设置显示格式 when Write_instr =>

LCD_RS <= '0'; --写??畲?

case cnt is

when 0 => data <= \写0x33

when 1 => data <= \

when 2 => data <= \写0x32 when 3 => data <= \

--0x28 功能设置:4位接口模式,2行显示

when 4 => data <= \ when 5 => data <= \

--0x06 模式设定: 输入后光标右移

when 6 => data <= \

when 7 => data <= \

--0x0c 显示设定:显示功能开,不显示光标,光标不闪烁

when 8 => data <= \ when 9 => data <= \

--0x01 清屏

when 10 => data <= \

when 11 => data <= \ when others => data <= \ end case; if(cnt=11)then cnt<=0;

state<=Set_AddrUp;

else

cnt<=cnt+1;

state<=Write_instr;

end if;

--设定显示地址

when Set_AddrUp=>

LCD_RS<='0';

if(cnt=0 or cnt=1 or cnt=2 or cnt=3)then

data <=\

elsif(cnt=4 or cnt=6 or cnt=8 or cnt=10)then

data <=\

end if;

state<=Set_AddrDown;

when Set_AddrDown=> case cnt is

when 0 => data <=\

when 1 => data <=\when 2 => data <=\


复杂数字电路设计实验报告_数字抢答器(4).doc 将本文的Word文档下载到电脑 下载失败或者文档不完整,请联系客服人员解决!

下一篇:毕业论文(设计)-矩阵初等变换及其应用

相关阅读
本类排行
× 注册会员免费下载(下载后可以自由复制和排版)

马上注册会员

注:下载文档有可能“只有目录或者内容不全”等情况,请下载之前注意辨别,如果您已付费且无法下载或内容有问题,请联系我们协助你处理。
微信: QQ: