Assignment 7
1. Analyze the sequential element (SE) of Actel ACT FPGA (as shown below) with any possible combinations of C1, C2 and CLR C controls. A. Which functions does this SE support?
B. Verify these functions by using HSPICE simulator at circuit level OR using Modelsim simulator at logic level.
Master LatchF11DC2C1CLRTG4G2Slave LatchF2S1G70S2QG80G5S1MG6G1MCcombinationallogic for clockand clear
Figure 1 Actel ACT 2 and ACT 3 Logic Modules: The equivalent circuit (without buffering) of the SE (sequential element)
Solution: A：
（1）、C1=0，C2=0，CLR=1，S1=0，D输出到M，同时将M传递到F1，G5处于采样阶段，而S2=1，所以G7处于保持状态；若CLR=0，G6和G8输出为0，整个电路不工作。
（2）、C1=1，C2=0，CLR=1，则S1=0，G5处于采样状态将信号传递到M，MC=1，M传输到F1，同时S2=0，则F1传递到S，同时也传递到Q，即直通状态，CLR=0也是如此状态，因为T=1。
（3）、C1=0，C2=1，CLR=1，由于MC=1，所以输出到F1，且S1=1，G5处于保持，而S2=0，所以F1传输到S，同时可以传递到Q，这个属于边沿触发器的传递阶段。若CLR=0，MC=0，所以都清0。
（4）、C1=1，C2=1，CLR=1，则S1=0，D输出到M，MC=1，所以M采样到F1，而G7则处于保持状态，CLR=0，若CLR=0，G6和G8输出为0，整个电路不工作。
观察以上四种情况，（1）与（4）状态相同，（2）属于直通状态具有一定延时，（3）处于G5保持，G7输出到Q。基于这样的情况，将（1）与（3）组合为一个上升沿D触发器，（4）与（3）组合成为一个下降沿D触发器；同时将（2）与（3）可以构成一个锁存器，在（2）的时候电平触发Q=D，（3）的时候保持Q的状态；以上几种状态在CLR=0时候都可以清零。 B：
A中已经基本的分析清楚了各种情况，这里只验证A中（1）与（3）组合为一个上升沿D触发器和直通状态（2）：
①、（1）与（3），则C1保持为0，C2为CLK时钟变化，VHDL代码如下： library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.std_logic_unsigned.ALL; library UNISIM;
G3use UNISIM.VComponents.all; entity ACT_FPGA is
Port ( D : in std_logic; C2 : in std_logic; C1 : in std_logic; CLR : in std_logic; Q : out std_logic); end ACT_FPGA;
architecture struct of ACT_FPGA is signal S1: std_logic; signal S2: std_logic; signal M: std_logic; signal F1: std_logic; signal MC: std_logic; signal T: std_logic; signal S: std_logic; signal F2: std_logic; begin U0: and2b1 port map (S1,C1,C2); --S1<=C2 and (not C1); U1: muxcy port map (M,F1,D,S1); U2: and2b1 port map (T,C2,C1); --T<=(not C2) and C1;
U3: or2 port map (MC,T,CLR); U4: xnor2 port map (S2,C2,C1); U5: and2 port map (F1,MC,M); U6: muxcy port map (S,F2,F1,S2); U7: and2 port map (F2,MC,S); Q <= F2; end struct;
TestBench如下： library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM;
use UNISIM.VComponents.all; ENTITY ACT_FPGA_TB IS END ACT_FPGA_TB;
ARCHITECTURE behavior OF ACT_FPGA_TB IS
-- Component Declaration for the Unit Under Test (UUT) COMPONENT ACT_FPGA PORT(
D : IN std_logic; C2 : IN std_logic; C1 : IN std_logic; CLR : IN std_logic; Q : OUT std_logic );
END COMPONENT; --Inputs
signal D : std_logic := '0'; signal C2 : std_logic := '0'; signal C1 : std_logic := '0'; signal CLR : std_logic := '0'; --Outputs
signal Q : std_logic := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ACT_FPGA PORT MAP ( D => D, C2 => C2, C1 => C1, CLR => CLR, Q => Q); -- Stimulus process stim_proc: process begin
--insert stimulus here ------------- Current Time: 100ns WAIT FOR 100 ns; D <= '1'; C1 <= '0'; C2 <= '0'; CLR <= '1';
-- ------------- Current Time: 200ns
WAIT FOR 100 ns; D <= '1'; C1 <= '0'; C2 <= '1'; CLR <= '1';
-- ------------- Current Time: 300ns WAIT FOR 100 ns; D <= '1'; C1 <= '0'; C2 <= '0';
CLR <= '1';
-- ------------- Current Time: 400ns WAIT FOR 100 ns; D <= '1'; C1 <= '0'; C2 <= '1'; CLR <= '1';
-- ------------- Current Time: 500ns WAIT FOR 100 ns; D <= '1'; C1 <= '0'; C2 <= '0'; CLR <= '1';
-- ------------- Current Time: 600ns WAIT FOR 100 ns; D <= '1'; C1 <= '0'; C2 <= '1'; CLR <= '1';
-- ------------- Current Time: 700ns WAIT FOR 100 ns; D <= '1'; C1 <= '0'; C2 <= '0'; CLR <= '1';
-- ------------- Current Time: 900ns WAIT FOR 100 ns; D <= '1'; C1 <= '0'; C2 <= '1'; CLR <= '1'; end process; END;
可以看到C2的低电平期间保持，并将F1看到为高，并在C2的上升沿，得到了Q输出为高电平，同时D变为0时，F1变为0，同时在C2的上升沿变为0。
②、（2）中是直通状态验证如下：
只需要改变TestBench的输入信号即可，得到验证波形如下：
可以看到输入D和输出Q完全一致，表明逻辑电路连接没问题，同时A中的分析也没有问题。验证完毕。
同理可以知道（4）与（3），则C2保持为1，C1为CLK时钟变化，而（2）与（3）则C1和C2电平始终相反，但是需要先’10’再’01’即可。
附件如下：RTL Schematic
2. (This exercise is taken from an MIT course.)The Xilinx 4000 series field-programmable gate array (FPGA) can be programmed to emulate a circuit made up of many thousands of gates; for example, the XC4025E can emulate circuits with up to 25,000 gates. The heart of the FPGA architecture is a configurable logic block (CLB) which has a combinational logic subsection with the following circuit diagram:
There are two 4-input function generators and one 3-input function generator, each capable of implementing an arbitrary Boolean function of its inputs.
The following is a list of the possible configurations. Show them by presenting their necessary control signals and the Boolean equations for the outputs of the form: X = F(F1,F2,F3,F4).
A. An arbitrary function F of up to four input variables, plus another arbitrary function G of
up to four unrelated input variables, plus a third arbitrary function H of up to three unrelated input variables.
B. An arbitrary single function of five variables.
C. An arbitrary function of four variables together with some functions of six variables.