基于FPGA 的六层电梯控制系统
end if;
end process controllift;
controllight:process(reset,buttonclk) begin
if reset='1' then stoplight<=\ elsif buttonclk'event and buttonclk='1' then
if clearup='1' then
stoplight(position)<='0';fuplight(position)<='0'; elsif f1upbutton='1' then fuplight(1)<='1'; elsif f2upbutton='1' then fuplight(2)<='1'; elsif f3upbutton='1' then fuplight(3)<='1'; elsif f4upbutton='1' then fuplight(4)<='1'; elsif f5upbutton='1' then fuplight(5)<='1';
end if; if cleardn='1' then
stoplight(position)<='0'; fdnlight(position)<='0'; elsif f2dnbutton='1' then fdnlight(2)<='1'; elsif f3dnbutton='1' then fdnlight(3)<='1'; elsif f4dnbutton='1' then fdnlight(4)<='1'; elsif f5dnbutton='1' then fdnlight(5)<='1'; elsif f6dnbutton='1' then fdnlight(6)<='1';
end if; if stop1button='1' then stoplight(1)<='1'; elsif stop2button='1' then stoplight(2)<='1'; elsif stop3button='1' then stoplight(3)<='1'; elsif stop4button='1' then stoplight(4)<='1'; elsif stop5button='1' then stoplight(5)<='1'; elsif stop6button='1' then stoplight(6)<='1';
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基于FPGA 的六层电梯控制系统
end if; end if;
end process controllight; end art; 分频器程序： library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity div is port(
clk_in:in std_logic; div_out:out std_logic ); end;
architecture a of div is
signal fre_N:integer range 0 to 10; signal clk_tmp:std_logic; begin
div_out<=clk_tmp; process(clk_in) begin
if falling_edge(clk_in) then if fre_N>10 then fre_N<=0;
clk_tmp<=not clk_tmp; else fre_N<=fre_N+1; end if;
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基于FPGA 的六层电梯控制系统
end if; end process; end a; 译码器程序： library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yima is port(
aaa:integer range 1 to 6;
bbb:out std_logic_vector(3 downto 0) ); end;
architecture a of yima is begin process(aaa) begin
if aaa=1 then bbb<=\ elsif aaa=2 then bbb<=\ elsif aaa=3 then bbb<=\ elsif aaa=4 then bbb<=\ elsif aaa=5 then bbb<=\ elsif aaa=6 then bbb<=\end if; end process; end a;
数据选择器程序： library ieee;
use ieee.std_logic_1164.all;
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基于FPGA 的六层电梯控制系统
entity led is port(
input:in std_logic_vector(3 downto 0); output:out std_logic_vector(6 downto 0) ); end;
architecture a of led is begin
process(input)
output<=\ \ \ \ \ \ \end process; end a;
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