architecture archmux of decode47 is begin
process(en,adr)
begin
if en='0' then
decodeout<=\可改为(others=>’0’) else
case adr is
when \ when \ when \ when \ when \ when \ when \ when \ when \ when others=> decodeout<= \ end case; end if;
end process; end archmux;
三-八译码器
LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
entity decoder is port(adrin : in std_logic_vector(2 downto 0); deout : out std_logic_vector(7 downto 0) ); end decoder;
architecture behave of decoder is begin
process(adrin)
variable tmp:std_logic_vector(7 downto 0); --此处不能定义为信号150
.
begin
tmp:=(others=>'0'); --others=>’0’表示将tmp的各位赋相同值“0”。 tmp(conv_integer(adrin)):='1'; --conv_integer函数在程序包std_logic_unsigned中定义
deout<=tmp; end process; end behave;
编码器
优先编码器(Priority encoder)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity encoder is
port(a,b,c,d,e,f,g,h : in std_logic; codeout : out std_logic_vector(2 downto 0) ); end encoder;
architecture behave of encoder is begin
codeout<=\when h='1' else \when g='1' else \when f='1' else \when e='1' else \when d='1' else \when c='1' else \when b='1' else \when a='1' else \end behave;
比较器
library ieee;
151
.
use ieee.std_logic_1164.all; ENTITY comp IS
PORT ( a,b :in std_logic_vector(3 downto 0); aqualb,agrdb,alessb :out std_logic ); END comp;
ARCHITECTURE behave OF comp IS BEGIN
aqualb<='1' when a=b else '0'; agrdb<='1' when a>b else '0'; alessb<='1' when a
MUX数据选择器
16路四选一
library ieee;
use ieee.std_logic_1164.all; entity v16mux4 is port
(datain0,datain1,datain2,datain3 :in std_logic_vector(15 downto 0); sel :in std_logic_vector(1 downto 0); dataout :out std_logic_vector(15 downto 0)); end v16mux4;
architecture archmux of v16mux4 is begin
with sel select
dataout<=datain0 when \ datain1 when \ datain2 when \ datain3 when others; end archmux;
152
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奇偶校验电路
library ieee;
use ieee.std_logic_1164.all; entity parity is
generic(bussize:integer:=8); --在调用此设计时，可重新指定此值，或默认值8； port
(databus :in std_logic_vector(bussize-1 downto 0); even_num,odd_num :out std_logic); end parity;
architecture behave of parity is begin
process(databus)
variable tmp :std_logic;
begin
tmp:='0';
for i in databus'low to databus'high loop --for—loop语句 tmp:=tmp xor databus(i); end loop;
odd_num<=tmp; even_num<=not tmp; end process; end behave;
三态输出电路
library ieee;
use ieee.std_logic_1164.all; entity triout is
generic(bussize:integer:=8); port
(data_in:in std_logic_vector(bussize-1 downto 0); oe_en :in std_logic;
data_out:out std_logic_vector(bussize-1 downto 0)); end triout;
153
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architecture behave of triout is
begin
data_out<=data_in when oe_en='1' else (others=>'Z'); --注意此处的“Z”要大写；
--因为在“std_logic”中作为枚举类型“Z”是以大写字母存在的。 end behave;
同步化电路
library ieee;
use ieee.std_logic_1164.all; ENTITY syncir IS
PORT ( sin,clk : IN std_logic; sout : out std_logic);
END syncir ;
ARCHITECTURE behave OF syncir IS signal q1,q0 : std_logic;
BEGIN
sout<=q0 and (not(q1)); PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN q0<=sin; q1<=q0; END IF; END PROCESS; END behave;
M=60的计数器
-- A asynchronous reset; synchronous load ;enable up; 8421BCD counter -- module=60; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY cntm60 IS PORT
154
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