( ci : IN std_logic; nreset : IN std_logic; load : IN std_logic; d : IN std_logic_vector(7 downto 0); clk : IN std_logic; co : out std_logic; qh : buffer std_logic_vector(3 downto 0); ql : buffer std_logic_vector(3 downto 0) ); END cntm60;
ARCHITECTURE behave OF cntm60 IS BEGIN
co<='1' when (qh=\and ql=\and ci='1') else '0'; PROCESS (clk,nreset) BEGIN IF(nreset='0') THEN qh<=\ ql<=\ ELSIF (clk'EVENT AND clk = '1') THEN if(load='1') then
qh<=d(7 downto 4); ql<=d(3 downto 0); elsif(ci='1') then if (ql=9) then ql<=\ if(qh=5) then qh<=\ else
qh<=qh+1; end if; else ql<=ql+1; end if;
END IF; --end if LOAD END IF; --end if _reset END PROCESS; END behave;
155
.
移位寄存器
--可左，右移，同步置数，同步清零 library ieee;
use ieee.std_logic_1164.all; ENTITY shifter IS
PORT (data :in std_logic_vector(7 downto 0); sl_in,sr_in,reset,clk : IN std_logic; mode :in std_logic_vector(1 downto 0); qout : buffer std_logic_vector(7 downto 0)); END shifter;
ARCHITECTURE behave OF shifter IS signal q1,q0 : std_logic;
BEGIN
PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN if(reset='1') then
qout<=(others=>'0'); --同步清零
else
case mode is when \
qout<=sr_in & qout(7 downto 1); --右移 when \
qout<=qout(6 downto 0) & sl_in; --左移
when \
qout<=data; --置数
when others=>null; --“NULL”表示无操作 end case; end if; END IF; END PROCESS; END behave;
156
.
堆栈（stack）
--该设计为一个有16个字，字长为8位的栈。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_signed.all;
ENTITY stack IS PORT ( datain : IN std_logic_vector(7 downto 0); push,pop,reset,clk : IN std_logic; stackfull : out std_logic; dataout : buffer std_logic_vector(7 downto 0)); END stack;
ARCHITECTURE a OF stack IS
type arraylogic is array (15 downto 0) of std_logic_vector(7 downto 0); signal data : arraylogic; --此处定义了data为一个数组16?8
signal stackflag:std_logic_vector(15 downto 0); BEGIN
stackfull<=stackflag(0);
PROCESS (clk,reset,pop,push)
variable selfunction : std_logic_vector(1 downto 0); BEGIN selfunction:=push & pop; if reset='1' then
stackflag<=(others=>'0'); dataout<=(others=>'0');
FOR i IN 0 to 15 LOOP data(i)<=(others=>'0'); END LOOP;
elsif clk'event and clk = '1' then case selfunction is
when \ --push data(15)<=datain;
stackflag<='1' & stackflag(15 downto 1); FOR i IN 0 to 14 LOOP data(i)<=data(i+1);
157
.
END LOOP; when \ --pop dataout<=data(15);
stackflag<=stackflag(14 downto 0) & '0';
FOR i IN 15 downto 1 LOOP data(i)<=data(i-1);
END LOOP;
when others=>NULL ;--in other cases, stack don't be changed end case; end if; END PROCESS; END a;
状态机（Mealy和Moore型）
如何进行状态编码可见2 Moore型状态机的设计部分。 1.Mealy型电路，以实现下面状态转移图为例
X/Z0/0reset=1，异步 1/11/01/01/0SASBSCSD0/00/0
单进程的状态机： library ieee;
use ieee.std_logic_1164.all;
ENTITY statem1 IS PORT( clk : IN STD_LOGIC; reset : IN STD_LOGIC; x : IN STD_LOGIC; z : OUT STD_LOGIC);
158
.
END statem1 ;
ARCHITECTURE behave OF statem1 IS TYPE STATE_TYPE IS (sa, sb, sc,sd); SIGNAL state: STATE_TYPE; BEGIN
PROCESS (clk,reset) BEGIN
IF reset = '1' THEN state <= sa;
ELSIF clk'EVENT AND clk = '1' THEN CASE state IS WHEN sa => IF x='1' THEN state <= sb; else
state<=sa; END IF;
WHEN sb => IF x='1' THEN state <= sc; else
state<=sa; END IF; WHEN sc => IF x='1' THEN
state<=sd; else
state<=sa; END IF; WHEN sd => IF x='1' THEN state <= sd; else
state<=sa; END IF; END CASE; END IF;
END PROCESS;
z<='1' when state=sd and x='1' else '0'; --输出不仅与状态有关，还与当前输入有关。 END behave;
159
.