parameter dat0=4'h4; parameter dat1=4'h5; parameter dat2=4'h6; parameter dat3=4'h7; parameter dat4=4'h8; parameter dat5=4'h9;
parameter dat6=4'hA; parameter dat7=4'hB; parameter dat8=4'hC; parameter dat9=4'hD; parameter dat10=4'hE; parameter dat11=5'h10;
always @(posedge clk) // 10MHZ begin
counter=counter+1; if(counter==16'h0005) clkr=~clkr; end
always @(posedge clkr ) begin
current=next; case(current)
set0: begin rs<=0; dat<=8'h30; next<=set1; end set1: begin rs<=0; dat<=8'h0c; next<=set2; end set2: begin rs<=0; dat<=8'h6; next<=set3; end set3: begin rs<=0; dat<=8'h1; next<=dat0; end dat0: begin rs<=1; dat<=\ dat1: begin rs<=1; dat<=\
dat2: begin rs<=1; dat<=\ dat3: begin rs<=1; dat<=\ dat4: begin
if(c==4'b0000) begin rs<=1; dat<=\ else if (c==4'b0001) begin rs<=1; dat<=\ else if (c==4'b0010) begin rs<=1; dat<=\ else if (c==4'b0011) begin rs<=1; dat<=\ else if (c==4'b0100) begin rs<=1; dat<=\ else if (c==4'b0101) begin rs<=1; dat<=\ else if (c==4'b0110) begin rs<=1; dat<=\ else if (c==4'b0111) begin rs<=1; dat<=\ else if (c==4'b1000) begin rs<=1; dat<=\ else if (c==4'b1001) begin rs<=1; dat<=\end
dat5: begin
if(b==4'b0000) begin rs<=1; dat<=\ else if (b==4'b0001) begin rs<=1; dat<=\ else if (b==4'b0010) begin rs<=1; dat<=\ else if (b==4'b0011) begin rs<=1; dat<=\ else if (b==4'b0100) begin rs<=1; dat<=\ else if (b==4'b0101) begin rs<=1; dat<=\ else if (b==4'b0110) begin rs<=1; dat<=\ else if (b==4'b0111) begin rs<=1; dat<=\ else if (b==4'b1000) begin rs<=1; dat<=\ else if (b==4'b1001) begin rs<=1; dat<=\end
dat6: begin rs<=1; dat<=\
dat7: begin
if(a==4'b0000) begin rs<=1; dat<=\
else if (a==4'b0001) begin rs<=1; dat<=\ else if (a==4'b0010) begin rs<=1; dat<=\ else if (a==4'b0011) begin rs<=1; dat<=\ else if (a==4'b0100) begin rs<=1; dat<=\ else if (a==4'b0101) begin rs<=1; dat<=\ else if (a==4'b0110) begin rs<=1; dat<=\ else if (a==4'b0111) begin rs<=1; dat<=\ else if (a==4'b1000) begin rs<=1; dat<=\ else if (a==4'b1001) begin rs<=1; dat<=\end
dat8: begin rs<=1; dat<=8'hdf; next<=dat9; end dat9: begin rs<=1; dat<=\
endcase
end
//assign en=clkr|e; assign en=clkr; assign rw=0; endmodule
//****************************温控模块***************************************// module Temperature(
input clk, // 50MHz时钟 //input rst_n, // 异步复位 inout one_wire, // One-Wire总线
output [15:0] temperature // 输出温度值 );
reg rst_n; reg [19:0]count; always@(posedge clk) begin
if(count<20'h80000) //? begin rst_n<=1;
count<=count+1; end
else if(count<20'h8ffff) //? begin rst_n<=0;
count<=count+1; end else
rst_n<=1; end
//++++++++++++++++++++++++++++++++++++++ // 分频器50MHz->1MHz 开始
//++++++++++++++++++++++++++++++++++++++ reg [5:0] cnt; // 计数子
always @ (posedge clk, negedge rst_n) if (!rst_n)
cnt <= 0; else
if (cnt == 49) cnt <= 0; else
cnt <= cnt + 1'b1;
reg clk_1us; // 1MHz 时钟
always @ (posedge clk, negedge rst_n) if (!rst_n) clk_1us <= 0; else
if (cnt <= 24) // 24 = 50/2 - 1 clk_1us <= 0; else
clk_1us <= 1;
//-------------------------------------- // 分频器50MHz->1MHz 结束 //--------------------------------------
//延时模块的使用
//++++++++++++++++++++++++++++++++++++++ // 延时模块 开始
//++++++++++++++++++++++++++++++++++++++ reg [19:0] cnt_1us; // 1us延时计数子 reg cnt_1us_clear; // 请1us延时计数子