基于FPGA的温控风扇(2) - 图文(7)

2019-03-23 11:46

end S6 : begin

cnt_1us_clear <= 0;

if (cnt_1us == 750000 | one_wire) // 延时750ms!!!! begin

cnt_1us_clear <= 1;

state <= S0; // 跳回S0,再次初始化 end end

S7 : begin // 读数据 if (step == 34) begin

bit_valid <= 0; one_wire_buf <= 0;

step <= step + 1'b1; state <= READ0; end

else if (step == 35) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1; state <= READ0; end

else if (step == 36) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1; state <= READ0; end

else if (step == 37) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1;

state <= READ0; end

else if (step == 38) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1;

state <= READ0; end

else if (step == 39) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1;

state <= READ0; end

else if (step == 40) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1;

state <= READ0; end

else if (step == 41) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1; state <= READ0; end

else if (step == 42) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1;

state <= READ0; end

else if (step == 43) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1; state <= READ0; end

else if (step == 44) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1;

state <= READ0;

end

else if (step == 45) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1;

state <= READ0; end

else if (step == 46) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1;

state <= READ0; end

else if (step == 47) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1;

state <= READ0; end

else if (step == 48) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1;

state <= READ0; end

else if (step == 49) begin

bit_valid <= bit_valid + 1'b1; one_wire_buf <= 0;

step <= step + 1'b1;

state <= READ0; //READ0通过一串指向后返回s7,结合step回到当前步骤数 end

else if (step == 50) begin

step <= 0; state <= S0; end

end

//++++++++++++++++++++++++++++++++ // 写状态机

//++++++++++++++++++++++++++++++++ WRITE0 : begin

cnt_1us_clear <= 0;

one_wire_buf <= 0; // 输出0 if (cnt_1us == 80) // 延时80us begin

cnt_1us_clear <= 1;

one_wire_buf <= 1'bZ; // 释放总线,自动拉高 state <= WRITE00; end


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