WHEN 96 => ToneIndex <= 8; WHEN 97 => ToneIndex <= 8; WHEN 98 => ToneIndex <= 8; WHEN 99 => ToneIndex <= 9; WHEN 100 => ToneIndex <= 12; WHEN 101 => ToneIndex <= 12; WHEN 102 => ToneIndex <= 12; WHEN 103 => ToneIndex <= 10; WHEN 104 => ToneIndex <= 9; WHEN 105 => ToneIndex <= 9; WHEN 106 => ToneIndex <= 10; WHEN 107 => ToneIndex <= 9; WHEN 108 => ToneIndex <= 8; WHEN 109 => ToneIndex <= 8; WHEN 110 => ToneIndex <= 6; WHEN 111 => ToneIndex <= 5; WHEN 112 => ToneIndex <= 3; WHEN 113 => ToneIndex <= 3; WHEN 114 => ToneIndex <= 3; WHEN 115 => ToneIndex <= 3; WHEN 116 => ToneIndex <= 8; WHEN 117 => ToneIndex <= 8; WHEN 118 => ToneIndex <= 8; WHEN 119 => ToneIndex <= 8; WHEN 120 => ToneIndex <= 6; WHEN 121 => ToneIndex <= 8; WHEN 122 => ToneIndex <= 6; WHEN 123 => ToneIndex <= 5; WHEN 124 => ToneIndex <= 3; WHEN 125 => ToneIndex <= 5; WHEN 126 => ToneIndex <= 6; WHEN 127 => ToneIndex <= 8; WHEN 128 => ToneIndex <= 5; WHEN 129 => ToneIndex <= 5; WHEN 130 => ToneIndex <= 5; WHEN 131 => ToneIndex <= 5; WHEN 132 => ToneIndex <= 5; WHEN 133 => ToneIndex <= 5; WHEN 134 => ToneIndex <= 5; WHEN 135 => ToneIndex <= 5;
WHEN 136 => ToneIndex <= 0; WHEN 137 => ToneIndex <= 0; WHEN 138 => ToneIndex <= 0; WHEN OTHERS => NULL;
-- 简谱休止符à输出-- 频率为零 END CASE; END PROCESS; END;
简谱码对应的分频预置数查表电路（ToneTaba.VHD）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY ToneTaba IS
PORT ( Index : IN INTEGER RANGE 0 TO 15; CODE : OUT INTEGER RANGE 0 TO 15; HIGH : OUT STD_LOGIC;
Tone : OUT INTEGER RANGE 0 TO 16#7FF# ); END;
ARCHITECTURE one OF ToneTaba IS BEGIN
Search : PROCESS(Index) BEGIN
CASE Index IS -- 译码电路，查表方式，控制音调的预置数 WHEN 0 => Tone <= 2047; CODE<=0; HIGH<='0'; WHEN 1 => Tone <= 773; CODE<=1; HIGH<='0'; WHEN 2 => Tone <= 912; CODE<=2; HIGH<='0'; WHEN 3 => Tone <= 1036; CODE<=3; HIGH<='0'; WHEN 5 => Tone <= 1197; CODE<=5; HIGH<='0'; WHEN 6 => Tone <= 1290; CODE<=6; HIGH<='0'; WHEN 7 => Tone <= 1372; CODE<=7; HIGH<='0'; WHEN 8 => Tone <= 1410; CODE<=1; HIGH<='1'; WHEN 9 => Tone <= 1480; CODE<=2; HIGH<='1'; WHEN 10 => Tone <= 1542; CODE<=3; HIGH<='1'; WHEN 12 => Tone <= 1622; CODE<=5; HIGH<='1'; WHEN 13 => Tone <= 1668; CODE<=6; HIGH<='1'; WHEN 15 => Tone <= 1728; CODE<=7; HIGH<='1'; WHEN OTHERS => NULL; END CASE; END PROCESS; END;
数控分频与演奏发生器（Speakera.VHD） LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY Speakera IS
PORT ( clk : IN STD_LOGIC;
Tone : IN INTEGER RANGE 0 TO 16#7FF#; SpkS : OUT STD_LOGIC ); END;
ARCHITECTURE one OF Speakera IS SIGNAL PreCLK : STD_LOGIC; SIGNAL FullSpkS : STD_LOGIC; BEGIN
DivideCLK : PROCESS(clk)
VARIABLE Count4 : INTEGER RANGE 0 TO 15; BEGIN
PreCLK <= '0';
-- 将CLK进行16分频，PreCLK为CLK的16分频 IF Count4 > 11 THEN PreCLK <= '1'; Count4 := 0;
ELSIF clk'EVENT AND clk = '1' THEN Count4 := Count4 + 1; END IF; END PROCESS;
GenSpkS : PROCESS(PreCLK, Tone)
VARIABLE Count11 : INTEGER RANGE 0 TO 16#7FF#; BEGIN
-- 11位可预置计数器
IF PreCLK'EVENT AND PreCLK = '1' THEN IF Count11 = 16#7FF# THEN Count11 := Tone;
FullSpkS <= '1'; ELSE
Count11 := Count11 + 1; FullSpkS <= '0'; END IF; END IF; END PROCESS;
DelaySpkS : PROCESS(FullSpkS) VARIABLE Count2 : STD_LOGIC; BEGIN
-- 将输出再进行2分频，将脉冲展宽，以使扬声器有足够功率发音 IF FullSpkS'EVENT AND FullSpkS = '1' THEN Count2 := NOT Count2;
IF Count2 = '1' THEN SpkS <= '1'; ELSE
SpkS <= '0'; END IF; END IF; END PROCESS; END;
三：系统以及各个模块的仿真波形
音乐节拍和音调发生器的仿真波形
简谱码对应的分频预置数查表电路仿真波形
音乐节拍和音调发生器仿真波形
数控分频与演奏发生器仿真波形
四：系统调试运行结果说明与分析
实验箱选择模式0。将设计出的演奏电路的程序经过编译（Compiler）后，选择FLEX10K系列中EPF10K10LC84-4作为目标器件（Assign/Device），并进行管脚锁定（Floorplan Editor）。器件编程(Programmer)，将编译生成的*.sof文件下载到目标芯片。实验箱自带蜂鸣器（Speaker）奏出“梁祝”的旋律，由此说明实验成功。
五：结论及体会
程序可以完成预定的功能，而且本系统还可以演奏出其他的曲子，只需将其简谱分频预置数写入ToneTaba.VHD，再将该曲子的节拍表输入到NoteTabs.VHD中，重新编译后，下载即可完成。通过这次实验，使我更加熟练的掌握了调制编译的过程，加深了对实验的兴趣。
（二）数字钟
一：系统功能概述
① 一个具有“时”、“分”、“秒”十进制数字显示（小时从00-23）计时器。 ② 具有手动校时、校分的功能。
二:系统组成以及系统各部分的设计
顶层文件(SHUZIZHONG.VHD)
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shuzizhong is
port(clk,set,change,s1,s2,s3:in std_logic;
second1,second2,minite1,minite2,hour1,hour2:out std_logic_vector(3 downto 0); cout:out std_logic); end entity;
architecture one of shuzizhong is begin
pro1:process(clk,set,s1,s2,s3,change) variable
msecond1,msecond2,mminite1,mminite2,mhour11,mhour12,mhour21,mhour22:std_logic_vector(3 downto 0); begin
if clk'event and clk='1' then
if set='1' then -----启动校验 if s1='1'
then msecond1:=msecond1+1; if msecond1=\
then msecond1:=\
msecond2:=msecond2+1; if msecond2=\ then msecond2:=\ end if; end if;
end if; --------秒校验 if s2='1' then
mminite1:=mminite1+1;
if mminite1=\