作中将任何非空单元写入“1”，这步骤需再编程之前进行。 读片内签名字节：
读签名字节的过程和单元030H、031H及032H的正常校验相仿，只需将P3.6和P3.7保持低电平，返回值意义如下： (030H)=1EH声明产品由ATMEL公司制造 (031H)=51H声明为AT89C51单片机 (032H)=FFH声明为12V编程电压 (032H)=05H声明为5V编程电压 编程接口：
采用控制信号的正确组合可对Flash闪速存储阵列中的每一代码字节进行写入和存储器的整片擦除，写操作周期是自身定时的，初始化后它将自动定时到操作完成。
AT89C51
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM) and 128 bytes of data random-access memory(RAM). The device is manufactured using
ATMEL Co.’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pin-out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the ATMEL Co.’s AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.
Features:
·Compatible with instruction set of MCS-51 products ·4K bytes of in-system reprogrammable Flash memory ·Endurance: 1000 write/erase cycles ·Fully static operation: 0 Hz to 24 MHz ·Three-level program memory lock ·128×8-bit internal RAM ·32 programmable I/O lines ·Two 16-bit Timer/Counters ·Six interrupt source ·Programmable serial channel
·Low-power idle and Power-down modes
Function Characteristic Description:
The AT89C51 provides the following standard features: 4K bytes of Flash memory, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
Pin Description:
·VCC: Supply voltage ·GND: Ground
·Port 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.
Port 0 may also be configured to be the multiplexed low order address/bus
during accesses to external program and data memory. In this mode P0 has internal pull ups.
Port 0 also receives the code bytes during Flash programming, and outputs the
code bytes during program verification. External pull ups are required during program verification.
·Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull ups.
Port 1 also receives the low-order address bytes during Flash programming
and verification.
·Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups.
Port 2 emits the high-order address byte during fetches from external program
memory and during accesses to external data memory which uses 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull ups when emitting 1s. During accesses to external data memory which uses 8-bit addresses (MOVX @ RI). Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals
during Flash programming and verification.
·Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull ups.
Port 3 also receives some control signals for Flash programming and
verification.
·RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
·ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN：Program Store Enable is the read strobe to external program memory. ·
When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
·EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during
Flash programming, for parts that require 12-volt VPP.
·XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
·XTAL2：Output from the inverting oscillator amplifier.
·Ready/BUSY: The progress of byte programming can also be monitored by the RDY/BSYoutput signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.
Oscillator Characteristics：
XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used.
To drive the device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven.
There are no requirements on the duty cycle of the external clock signal, since
the input to the internal clocking circuitry is through a divide by two flip trigger, but minimum and maximum voltage high and low time specifications must be observed.
Idle Mode：
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals
remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset,