the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
Power-down Mode:
In the power-down mode, the oscillator is stopped, and the instruction that
invokes power-down is the last instruction executed. The on-chip RAM and special function registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the special function registers but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Program Memory Lock Bits:
When lock bit 1 is programmed, the logic level at the EA pin is sampled and
latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.
Programming the Flash:
The AT89C51 is normally shipped with the on-chip Flash memory array in the
erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled.
The AT89C51 code memory array is programmed byte-by-byte in either
programming mode. To program any nonblank byte in the on-chip Flash memory, the entire memory must be erased using the chip erase mode.
Programming Algorithm:
Before programming the AT89C51, the address, data and control signals
should be set up according to the Flash programming mode table .To program the AT89C51, take the following steps:
1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming mode.
5. Pulse ALE/PROGonce to program a byte in the Flash array or the lock bits.
The byte-write cycle is self-timed and typically takes no more than 1.5ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.
Data Polling:
The AT89C51 features Data Polling to indicate the end of a write cycle.
During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data polling may begin any time after a write cycle has been initiated.
Program Verify:
If lock bits LB1 and LB2 have not been programmed, the programmed code
data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.
Chip Erase:
The entire Flash array is erased electrically by using the proper combination of
control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.
Reading the Signature Bytes:
The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows:
(030H) = 1EH indicates manufactured by ATMEL (031H) = 51H indicates AT89C51 single-chip (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming
Programming Interface:
Every code byte in the Flash array can be written and the entire array can be
erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion.