第八章 可综合的Verilog HDL设计实例
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第一阶段：先对构成RISC_CPU模型的各个子模块，如状态控制机模块（包括machine模块，machinectl模块）、指令寄存器模块（register模块）、算术逻辑运算单元模块（alu模块）等，分别加以综合以检查其可综合性，综合后及时进行后仿真，这样便于及时发现错误，及时改进。
DATA<7..0>\\I 12P 11P DATA<7..0> 1P CLK RD\\I RD 5P RST WR\\I WR 6P RSC HALT\\I HALT 7P ADDR<12..0>\\I ADDR<12..0> 8P 图8.5.2 用于综合的RISC_CPU模块（RSC）
第二阶段：把要综合的模块从仿真测试信号模块和虚拟外围电路模型（如ROM模块、RAM模块、显示部件模块等）中分离出来，组成一个独立的模块，其中包括了所有需要综合的模块。然后给这个大模块起一个名字，如本章中的例子，我们要综合的只是RISC_CPU并不包括虚拟外围电路，可以给这一模块起一个名字，例如称它为RSC_CHIP模块。如用电路图描述的话，我们还需给它的引脚加上标准的引脚部件并加标记，见图8.5.2。
第三阶段：加载需要综合的模块到综合器，本例所使用的综合器是 Synplify, 选定的 FPGA 是 Altera FLEX10K，针对它的库进行综合。
综合器综合的结果会产生一系列的文件，其中有一个文件报告用了所使用的基本单元，各部件的时间参数以及综合的过程。见下面的报告,它就是这个RISC_CPU芯片所用的综合报告，综合所用的库为Altera FLEX10K系列的FPGA库。
$ Start of Compile
#Fri Jul 21 10:11:03 2000
Synplify Verilog Compiler, version 5.2.2, built Aug 20 1999 Copyright (C) 1994-1999, Synplicity Inc. All Rights Reserved
@I::\
Verilog syntax check successful! Selecting top level module cpu Synthesizing module clk_gen Synthesizing module register Synthesizing module accum Synthesizing module alu
Synthesizing module machinect1 Synthesizing module machine Synthesizing module datactl
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第八章 可综合的Verilog HDL设计实例
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Synthesizing module adr
Synthesizing module counter Synthesizing module cpu @END
Process took 0.491 seconds realtime, 0.54 seconds cputime
Synplify Altera Technology Mapper, version 5.2.2, built Aug 31 1999 Copyright (C) 1994-1998, Synplicity Inc. All Rights Reserved Loading timing data for chip EPF10K10-3 List of partitions to map: view:work.cpu(verilog)
Automatic dissolve at startup in view:work.cpu(verilog) of m_counter(counter) Automatic dissolve at startup in view:work.cpu(verilog) of m_adr(adr)
Automatic dissolve at startup in view:work.cpu(verilog) of m_datactl(datactl)
Automatic dissolve at startup in view:work.cpu(verilog) of m_machinec1(machinect1) @N:\m_counter.pc_addr[12:0]
Automatic dissolve during optimization of view:work.cpu(verilog) of m_alu(alu)
Automatic dissolve during optimization of view:work.cpu(verilog) of m_accum(accum) Loading timing data for chip EPF10K10-3
Found clock m_machine.inc_pc with period 100ns Found clock m_clk_gen.fetch with period 100ns Found clock m_clk_gen.alu_clk with period 100ns Found clock clk with period 100ns ##### START TIMING REPORT #####
Set the Environment Variable SYNPLIFY_TIMING_REPORT_OLD to get the old timing report Performance Summary *********************
Requested Estimated Requested Estimated Clock Frequency Frequency Period Period Slack ----------------------------------------------------------------------------------- m_machine.inc_pc 10.0 MHz 95.2 MHz 100.0 10.5 89.5 m_clk_gen.alu_clk 10.0 MHz 59.5 MHz 100.0 16.8 83.2 clk 10.0 MHz 16.8 MHz 100.0 59.5 40.5 =================================================================================== Interface Information ***********************
Input Ports:
Port Reference User Arrival Required Name Clock Constraint Time Time Slack ----------------------------------------------------------------------------------------
clk System 0.0 0.0 >2000.0 NA data[0] m_clk_gen.alu_clk [rising] 0.0 0.0 85.9 85.9 data[1] m_clk_gen.alu_clk [rising] 0.0 0.0 86.2 86.2 data[2] m_clk_gen.alu_clk [rising] 0.0 0.0 86.5 86.5
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第八章 可综合的Verilog HDL设计实例
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data[3] m_clk_gen.alu_clk [rising] 0.0 0.0 87.0 87.0 data[4] m_clk_gen.alu_clk [rising] 0.0 0.0 88.8 88.8 data[5] m_clk_gen.alu_clk [rising] 0.0 0.0 89.1 89.1 data[6] m_clk_gen.alu_clk [rising] 0.0 0.0 89.4 89.4 data[7] m_clk_gen.alu_clk [rising] 0.0 0.0 89.9 89.9 reset clk [falling] 0.0 0.0 91.9 91.9 ========================================================================================
Output Ports:
Port Reference User Arrival Required Name Clock Constraint Time Time Slack -----------------------------------------------------------------------------------------
addr[0] clk [falling] 0.0 6.9 100.0 93.1 addr[1] clk [falling] 0.0 6.9 100.0 93.1 addr[2] clk [falling] 0.0 6.9 100.0 93.1 addr[3] clk [falling] 0.0 6.9 100.0 93.1 addr[4] clk [falling] 0.0 6.9 100.0 93.1 addr[5] clk [falling] 0.0 6.9 100.0 93.1 addr[6] clk [falling] 0.0 6.9 100.0 93.1 addr[7] clk [falling] 0.0 6.9 100.0 93.1 addr[8] clk [falling] 0.0 6.9 100.0 93.1 addr[9] clk [falling] 0.0 6.9 100.0 93.1 addr[10] clk [falling] 0.0 6.9 100.0 93.1 addr[11] clk [falling] 0.0 6.9 100.0 93.1 addr[12] clk [falling] 0.0 6.9 100.0 93.1 data[0] m_clk_gen.alu_clk [rising] 0.0 0.0 100.0 100.0 data[1] m_clk_gen.alu_clk [rising] 0.0 0.0 100.0 100.0 data[2] m_clk_gen.alu_clk [rising] 0.0 0.0 100.0 100.0 data[3] m_clk_gen.alu_clk [rising] 0.0 0.0 100.0 100.0 data[4] m_clk_gen.alu_clk [rising] 0.0 0.0 100.0 100.0 data[5] m_clk_gen.alu_clk [rising] 0.0 0.0 100.0 100.0 data[6] m_clk_gen.alu_clk [rising] 0.0 0.0 100.0 100.0 data[7] m_clk_gen.alu_clk [rising] 0.0 0.0 100.0 100.0 halt clk [rising] 0.0 1.0 100.0 99.0 rd clk [rising] 0.0 1.0 100.0 99.0 wr clk [rising] 0.0 1.0 100.0 99.0 ================================================================================== Detailed Timing Report for clock : clk ******************************************* Requested Period 100.0 ns Estimated Period 59.5 ns Worst Slack 40.5 ns
Start Points for Paths with Slack Worse than 42.8 ns :
Arrival Instance Type Pin Net Time Slack ---------------------------------------------------------------------------------
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m_machine.load_ir S_DFF Q m_machine.load_ir 51.4 40.5 m_machine.load_acc S_DFF Q m_machine.load_acc 51.0 41.1 =================================================================================
End Points for Paths with Slack Worse than 42.8 ns :
Required Instance Type Pin Net Time Slack ----------------------------------------------------------------------------------------------
m_register.opc_iraddr[8] S_DFFE ENA m_register.un1_un1_rst 97.8 40.5 m_register.opc_iraddr[7] S_DFFE ENA m_register.un1_un1_rst 97.8 40.5 m_register.opc_iraddr[6] S_DFFE ENA m_register.un1_un1_rst 97.8 40.5 m_register.opc_iraddr[5] S_DFFE ENA m_register.un1_un1_rst 97.8 40.5 m_register.opc_iraddr[4] S_DFFE ENA m_register.un1_un1_rst 97.8 40.5 m_register.opc_iraddr[3] S_DFFE ENA m_register.un1_un1_rst 97.8 40.5 m_register.opc_iraddr[2] S_DFFE ENA m_register.un1_un1_rst 97.8 40.5 m_register.opc_iraddr[1] S_DFFE ENA m_register.un1_un1_rst 97.8 40.5 m_register.opc_iraddr[15] S_DFFE ENA m_register.un1_un1_rst 97.8 40.5 m_register.opc_iraddr[14] S_DFFE ENA m_register.un1_un1_rst 97.8 40.5 ==================================================================================
A Critical Path with worst case slack = 40.5 ns:
Instance/Net Pin Pin Arrival Delta Fan Name Type Name Dir Time Delay Out ---------------------------------------------------------------------------------- m_machine.load_ir S_DFF Q Out 51.4 51.4 m_machine.load_ir Net 2 m_register.un1_un1_rst S_LUT I1 In 51.4 m_register.un1_un1_rst S_LUT OUT Out 57.3 5.9 m_register.un1_un1_rst Net 16 m_register.opc_iraddr[0] S_DFFE ENA In 57.3 ================================================================================== Setup requirement on this path is 2.2 ns. Detailed Timing Report for clock : m_clk_gen.alu_clk ******************************************* Requested Period 100.0 ns Estimated Period 16.8 ns Worst Slack 83.2 ns
Start Points for Paths with Slack Worse than 85.5 ns :
Arrival Instance Type Pin Net Time Slack ----------------------------------------------------------------------------------- m_accum.accum[1] S_DFFE Q m_accum.accum[1] 3.0 83.2 m_accum.accum[0] S_DFFE Q m_accum.accum[0] 2.6 83.3 m_accum.accum[2] S_DFFE Q m_accum.accum[2] 2.6 83.9 m_accum.accum[3] S_DFFE Q m_accum.accum[3] 2.6 84.4
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m_register.opc_iraddr[14] S_DFFE Q m_register.opc_iraddr[14] 4.4 85.5 ===================================================================================
End Points for Paths with Slack Worse than 85.5 ns :
Required Instance Type Pin Net Time Slack ----------------------------------------------------------------------------------- m_alu.alu_out[3] S_DFF D m_alu.alu_out_11_5[3] 97.8 83.2 m_alu.alu_out[2] S_DFF D m_alu.alu_out_11_5[2] 97.8 83.5 m_alu.alu_out[0] S_DFF D m_alu.alu_out_11_5[0] 97.8 84.4 m_alu.alu_out[7] S_DFF D m_alu.alu_out_11_5[7] 97.8 84.9 m_alu.alu_out[6] S_DFF D m_alu.alu_out_11_5[6] 97.8 85.2 m_alu.alu_out[5] S_DFF D m_alu.alu_out_11_5[5] 97.8 85.5 ===================================================================================
A Critical Path with worst case slack = 83.2 ns:
Instance/Net Pin Pin Arrival Delta Fan Name Type Name Dir Time Delay Out ----------------------------------------------------------------------------------- m_accum.accum[1] S_DFFE Q Out 3.0 3.0 m_accum.accum[1] Net 6 m_alu.un2_alu_out_add1 S_CAR I1 In 3.0 m_alu.un2_alu_out_add1 S_CAR COUT Out 4.2 1.2 m_alu.un2_alu_out_carry_1 Net 1 m_alu.un2_alu_out_add2 S_CAR CIN In 4.2 m_alu.un2_alu_out_add2 S_CAR COUT Out 4.5 0.3 m_alu.un2_alu_out_carry_2 Net 1 m_alu.un2_alu_out_add3 S_CAR CIN In 4.5 m_alu.un2_alu_out_add3 S_CAR OUT Out 6.7 2.2 m_alu.un2_alu_out_add3 Net 1 m_alu.alu_out_11_1[3] S_LUT I1 In 6.7 m_alu.alu_out_11_1[3] S_LUT OUT Out 9.6 2.9 m_alu.alu_out_11_1[3] Net 1 m_alu.alu_out_11_2[3] S_LUT I2 In 9.6 m_alu.alu_out_11_2[3] S_LUT OUT Out 12.5 2.9 m_alu.alu_out_11_2[3] Net 1 m_alu.alu_out_11_5[3] S_LUT I1 In 12.5 m_alu.alu_out_11_5[3] S_LUT OUT Out 14.6 2.1 m_alu.alu_out_11_5[3] Net 1 m_alu.alu_out[3] S_DFF D In 14.6 =================================================================================== Setup requirement on this path is 2.2 ns. Detailed Timing Report for clock : m_machine.inc_pc ******************************************* Requested Period 100.0 ns Estimated Period 10.5 ns Worst Slack 89.5 ns
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