第八章 可综合的Verilog HDL设计实例
----------------------------------------------------------------------------------------------------------------------
Start Points for Paths with Slack Worse than 91.8 ns :
Arrival Instance Type Pin Net Time Slack ----------------------------------------------------------------------------------------------
m_machine.load_pc S_DFF Q m_machine.load_pc 1.0 89.5 m_counter.pc_addr[0] S_DFF Q m_counter.pc_addr[0] 1.4 90.5 m_counter.pc_addr[1] S_DFF Q m_counter.pc_addr[1] 1.4 90.8 m_register.opc_iraddr[0] S_DFFE Q m_register.opc_iraddr[0] 1.8 91.0 m_register.opc_iraddr[1] S_DFFE Q m_register.opc_iraddr[1] 1.8 91.0 m_register.opc_iraddr[2] S_DFFE Q m_register.opc_iraddr[2] 1.8 91.0 m_register.opc_iraddr[3] S_DFFE Q m_register.opc_iraddr[3] 1.8 91.0 m_register.opc_iraddr[4] S_DFFE Q m_register.opc_iraddr[4] 1.8 91.0 m_register.opc_iraddr[5] S_DFFE Q m_register.opc_iraddr[5] 1.8 91.0 m_register.opc_iraddr[6] S_DFFE Q m_register.opc_iraddr[6] 1.8 91.0 ===================================================================================
End Points for Paths with Slack Worse than 91.8 ns :
Required Instance Type Pin Net Time Slack ----------------------------------------------------------------------------------- m_counter.pc_addr[0] S_DFF D m_counter.pc_addr_lm0 97.8 89.5 m_counter.pc_addr[1] S_DFF D m_counter.pc_addr_lm1 97.8 89.5 m_counter.pc_addr[2] S_DFF D m_counter.pc_addr_lm2 97.8 89.5 m_counter.pc_addr[3] S_DFF D m_counter.pc_addr_lm3 97.8 89.5 m_counter.pc_addr[4] S_DFF D m_counter.pc_addr_lm4 97.8 89.5 m_counter.pc_addr[5] S_DFF D m_counter.pc_addr_lm5 97.8 89.5 m_counter.pc_addr[6] S_DFF D m_counter.pc_addr_lm6 97.8 89.5 m_counter.pc_addr[7] S_DFF D m_counter.pc_addr_lm7 97.8 89.5 m_counter.pc_addr[8] S_DFF D m_counter.pc_addr_lm8 97.8 89.5 m_counter.pc_addr[9] S_DFF D m_counter.pc_addr_lm9 97.8 89.5 ===================================================================================
A Critical Path with worst case slack = 89.5 ns:
Instance/Net Pin Pin Arrival Delta Fan Name Type Name Dir Time Delay Out -------------------------------------------------------------------------------- m_machine.load_pc S_DFF Q Out 1.0 1.0 m_machine.load_pc Net 1 m_machine.load_pc_i S_LUT I0 In 1.0 m_machine.load_pc_i S_LUT OUT Out 6.8 5.8 m_machine.load_pc_i Net 13 m_counter.pc_addr_lm0 S_MUX21 SEL In 6.8 m_counter.pc_addr_lm0 S_MUX21 Z Out 8.3 1.5 m_counter.pc_addr_lm0 Net 1 m_counter.pc_addr[0] S_DFF D In 8.3 ================================================================================ Setup requirement on this path is 2.2 ns.
206
第八章 可综合的Verilog HDL设计实例
----------------------------------------------------------------------------------------------------------------------
##### END TIMING REPORT #####
--------------------------------------- Resource Usage Report
Synplify is performing all technology mapping
Post place and route resource use may vary a small
amount due to logic cell replication and register packing decisions during place and route.
Design view:work.cpu(verilog) Selecting part epf10k10lc84-3
Logic resources: 149 LCs of 576 (25%) Number of Nets: 265 Number of Inputs: 926
Register bits: 69 (26 using enable) I/O cells: 26
Details:
Cells in logic mode: 116 Cells in arith mode: 8 Cells in cascade mode: 10 Cells in counter mode: 13
DFFs with no logic: 2 (uses cell for routing) LUTs driving both DFF and logic: 2
Found clock clk with period 100ns
Found clock alu_clk with period 100ns Found clock fetch with period 100ns Found clock inc_pc with period 100ns
Enabling timing driven placement for new ACF file. All Constraints processed! Mapper successful!
Process took 7.03 seconds realtime, 7.1 seconds cputime
//-------------------- RISC_CPU芯片综合结果报告结束---------------------------
8.5.3.RISC_CPU模块的优化和布局布线
选定部件库后就可以对所设计的RISC_CPU模型进行综合，综合后产生了一系列的文件，其中XXXXX.edf 文件就是与所选定的厂家部件库对应的电子设计交换格式（Electronic Design
Interchange Format）文件或是与某一类部件库（如通用FPGA库）对应的电子设计交换格式文件，这也就是在电路设计工业界常说的EDIF格式文件。在产生了XXXXX.edf文件之后，就要进行后仿真。以下介绍的是Altera Max+II 9.3 进行布线，在使用时在软件相应项选取所得到的cpu.edf文件，相对应的部件库（Altera FLEX10K）以及输出格式（verilog）。布线完成后得到两个文件cpu.vo和alt_max2.vo。 cpu.vo是所设计的RISC_CPU的门级结构，即利用Verilog 语法描述的用alt_max2部件库中的基本元件构成的复杂电路连线网络，而alt_max2.vo是cpu.vo所引用的门级模型的库文
207
第八章 可综合的Verilog HDL设计实例
----------------------------------------------------------------------------------------------------------------------
件，包含各种基本类型的电路的门级模型，它们的参数与真实器件完全一致，包括如延迟等参数。将这两个文件包含在cputop.v中，来代替原来的RTL级子模块，用仿真器再进行一次仿真，此时称为后仿真。实际上，后仿真与前仿真的根本区别在于测试文件所包含的模型的结构不同。前仿真使用的是一种RTL级模型，如cpu.v,而后仿真使用的是门级结构模型，其中不但有逻辑关系还包含实际门级电路和布线的延迟，还有驱动能力的问题。仔细观察后仿真波形就会发现与前仿真相比较，各信号的变化与时钟沿之间存在着延迟，这在前仿真时并未反映出来。
后仿真波形
下面的Verilog程序是由布局布线工具生成的，分别命名为cpu.vo和alt_max2.vo。由于cpu.vo是门级描述，共有上千行，而alt_max2.vo是仿真用库用UDP描述，也有几百行，无法在课本上全部列出，只能从中截取一小片段供同学参考。有兴趣的同学可以用 Verilog 语法中有关门级描述和用户自定义源语（UDP）来理解，由于是门级模型，又有布线的延迟，所以可以来验证电路结构是否符合设计要求。
/********************cpu.vo开始************************ // MAX+plus II Version 9.3 RC3 7/20/1999 // Sun Jul 30 10:53:36 2000 //
`timescale 100 ps / 100 ps
module cpu ( addr, data, CLK, reset, halt, rd, wr);
output [12:0] addr; inout [7:0] data; input CLK; input reset; output halt; output rd; output wr; supply0 gnd;
208
第八章 可综合的Verilog HDL设计实例
----------------------------------------------------------------------------------------------------------------------
supply1 vcc;
wire
\\|accum:m_accum|accum_0_.CLK , \\|accum:m_accum|accum_0_.D , \\|accum:m_accum|accum_0_.ENA ,
\\|accum:m_accum|accum_0__Q , \\|accum:m_accum|accum_1_.CLK , \\|accum:m_accum|accum_1_.D ,
… … …
TRIBUF0_cpu TRIBUF_2
( .Y(data[0]), .IN1(N_126), .OE(\\|datactl:m_datactl|data_0_.OE ) );
TRIBUF0_cpu TRIBUF_4
( .Y(data[1]), .IN1(N_135), .OE(\\|datactl:m_datactl|data_1_.OE ) );
TRIBUF0_cpu TRIBUF_6
( .Y(data[2]), .IN1(N_144), .OE(\\|datactl:m_datactl|data_2_.OE ) );
TRIBUF0_cpu TRIBUF_8
( .Y(data[3]), .IN1(N_153), .OE(\\|datactl:m_datactl|data_3_.OE ) );
… …
AND1 AND1_49 ( \\|datactl:m_datactl|data_0_.OE , N_124 );
DELAY DELAY_50 ( N_124, \\|machine:m_machine|datactl_ena1_Q ); defparam DELAY_50.TPD = 40;
DELAY DELAY_51 ( N_126, N_127 );
XOR2 XOR2_52 ( N_127, N_128, N_132 ); ….
module DFF0_cpu ( Q, D, CLK, CLRN, PRN ); input D; input CLK; input CLRN; input PRN; output Q;
PRIM_DFF (Q, D, CLK, CLRN, PRN);
wire legal;
and(legal, CLRN, PRN); specify
specparam TREG = 9; specparam TRSU = 13; specparam TRH = 14; specparam TRPR = 10; specparam TRCL = 10;
$setup ( D, posedge CLK &&& legal, TRSU ) ; $hold ( posedge CLK &&& legal, D, TRH ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL ) ; ( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR ) ; ( posedge CLK => (Q +: D)) = ( TREG, TREG ) ;
209
第八章 可综合的Verilog HDL设计实例
----------------------------------------------------------------------------------------------------------------------
endspecify endmodule … …
/******************cpu.vo结束********************
/*****************alt_max2.vo开始**************** //
// MAX+plus II Version 9.3 RC3 7/20/1999 // Sun Jul 30 10:53:36 2000 //
//`define SDF_IOPATH
`timescale 100 ps / 100 ps
primitive PRIM_DFF (Q, D, CP, RB, SB);
output Q;
input D, CP, RB, SB; reg Q;
initial Q = 1'b0;
// FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW // ASYNCHRONOUS SET AND CLEAR. ( Q OUTPUT UDP ).
table
// D CP RB SB : Qt : Qt+1
1 (01) 1 1 : ? : 1; // clocked data 1 (01) 1 x : ? : 1; // pessimism
1 ? 1 x : 1 : 1; // pessimism
0 0 1 x : 1 : 1; // pessimism 0 x 1 (?x) : 1 : 1; // pessimism 0 1 1 (?x) : 1 : 1; // pessimism …….
primitive PRIM_LATCH (Q, ENA, D); input D; input ENA;
output Q; reg Q;
table
// ENA D Q Q+ 0 ? : ? : -; 1 0 : ? : 0;
210