4'b0101: c=8'b10010010; 4'b0110: c=8'b10000010; 4'b0111: c=8'b11111000; 4'b1000: c=8'b10000000; 4'b1001: c=8'b10010000; 4'b1010: c=8'b10001000; 4'b1011: c=8'b10000011; 4'b1100: c=8'b11000110; 4'b1101: c=8'b10100001; 4'b1110: c=8'b10000110; 4'b1111: c=8'b10001110; //f endcase end
endmodule buzzer
向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调，该实验通过设计一个状态机和分频
器使蜂鸣器发出\多来咪发梭拉西多\的音调。 module buzzer(clk,rst,out); input clk,rst; output out; reg out;
reg[3:0] clk_div1; //基频分频计数器，基频为4M
reg[12:0] clk_div2;//音阶分频计数器，由基频分频产生各个音阶 reg[21:0] cnt;//各音阶发声时间长短计数器 reg[2:0] state;
parameter duo=3822, //各个音调的分频系数 lai=3405, mi=3034, fa=2865, suo=2551, la=2273, xi=2024,
duo1=1911;
always@(posedge clk or negedge rst) begin if(!rst) begin clk_div1<=0; end else begin if(clk_div1!=9) clk_div1<=clk_div1+1; else clk_div1<=0; end end
always@(posedge clk or negedge rst) begin if(!rst) begin clk_div2<=0; state<=0; cnt<=0; out<=0; end else if(clk_div1==9) begin case(state) 3'b000: begin //发“多” cnt<=cnt+1; if(cnt==22'h3fffff) state<=3'b001; if(clk_div2!=duo) clk_div2<=clk_div2+1; else begin clk_div2<=0; out<=~out; end end 3'b001: begin //发“来” cnt<=cnt+1; if(cnt==22'h3fffff) state<=3'b010; if(clk_div2!=lai) clk_div2<=clk_div2+1; else begin clk_div2<=0; out<=~out; end
end
3'b010:begin //发\米“ cnt<=cnt+1; if(cnt==22'h3fffff) state<=3'b011; if(clk_div2!=mi) clk_div2<=clk_div2+1; else begin clk_div2<=0; out<=~out; end end
3'b011: begin //发\法“ cnt<=cnt+1; if(cnt==22'h3fffff) state<=3'b100; if(clk_div2!=fa) clk_div2<=clk_div2+1; else begin clk_div2<=0; out<=~out; end end
3'b100: begin //发\梭“ cnt<=cnt+1; if(cnt==22'h3fffff) state<=3'b101; if(clk_div2!=suo) clk_div2<=clk_div2+1; else begin clk_div2<=0; out<=~out; end end
3'b101: begin //发\拉“ cnt<=cnt+1; if(cnt==22'h3fffff) state<=3'b110; if(clk_div2!=la) clk_div2<=clk_div2+1; else begin clk_div2<=0; out<=~out; end
end 3'b110: begin //发\西“ cnt<=cnt+1; if(cnt==22'h3fffff) state<=3'b111; if(clk_div2!=xi) clk_div2<=clk_div2+1; else begin clk_div2<=0; out<=~out; end end 3'b111: begin //发\多“（高音） cnt<=cnt+1; if(cnt==22'h3fffff) state<=3'b000; if(clk_div2!=duo1) clk_div2<=clk_div2+1; else begin clk_div2<=0; out<=~out; end end endcase end end
endmodule LCD1602_B
//www.21eda.com
//本实验是用LCD1602显示英文。（LCD带字库） module lcd(clk, rs, rw, en,dat);
input clk; //系统时钟输入50M output [7:0] dat; //LCD的8位数据口 output rs,rw,en; //LCD的控制脚 reg e;
reg [7:0] dat; reg rs;
reg [15:0] counter; reg [4:0] current,next; reg clkr; reg [1:0] cnt;
parameter set0=4'h0; parameter set1=4'h1; parameter set2=4'h2;
parameter set3=4'h3; parameter dat0=4'h4; parameter dat1=4'h5; parameter dat2=4'h6; parameter dat3=4'h7; parameter dat4=4'h8; parameter dat5=4'h9;
parameter dat6=4'hA; parameter dat7=4'hB; parameter dat8=4'hC; parameter dat9=4'hD; parameter dat10=4'hE; parameter dat11=5'h10; parameter nul=4'hF;
always @(posedge clk) begin
counter=counter+1; if(counter==16'h000f) clkr=~clkr; end
always @(posedge clkr) begin
current=next; case(current)
set0: begin rs<=0; dat<=8'h31; next<=set1; end //*设置8位格式,2行,5*7*
set1: begin rs<=0; dat<=8'h0C; next<=set2; end //*整体显示,关光标,不闪烁*/ set2: begin rs<=0; dat<=8'h6; next<=set3; end //*设定输入方式,增量不移位*/ set3: begin rs<=0; dat<=8'h1; next<=dat0; end //*清除显示*/ //上面是LCD的初始化
dat0: begin rs<=1; dat<=8'h3C; next<=dat1; end dat1: begin rs<=1; dat<=\ dat2: begin rs<=1; dat<=\ dat3: begin rs<=1; dat<=\ dat4: begin rs<=1; dat<=\ dat5: begin rs<=1; dat<=8'h3E; next<=dat6; end dat6: begin rs<=1; dat<=\ dat7: begin rs<=1; dat<=\ dat8: begin rs<=1; dat<=\ dat9: begin rs<=1; dat<=\ dat10: begin rs<=1; dat<=\ dat11: begin rs<=1; dat<=\
//上面是在这12个状态中要显示的字符 FPGA GOOD!!
nul: begin rs<=0; dat<=8'h00; //行一遍 然后 把液晶的E 脚 拉高