verilog HDL基础程序(3)

2019-04-09 20:32

if(cnt!=2'h2) begin

e<=0;next<=set0;cnt<=cnt+1; end else

begin next<=nul; e<=1; end end default: next=set0; endcase end

assign en=clkr|e; assign rw=0; endmodule

LCD12864显示汉字

//利用VHDL驱动LCD12864

//视频教程适合我们21EDA电子的所有学习板) //本实验是用LCD12864显示汉字。(LCD带字库) module LCD12864 (clk, rs, rw, en,dat); input clk; //系统时钟输入50M output [7:0] dat; //LCD的8位数据口 output rs,rw,en; //LCD的控制脚 reg e;

reg [7:0] dat; reg rs;

reg [15:0] counter; reg [6:0] current,next; reg clkr; reg [1:0] cnt;

parameter set0=6'h0; parameter set1=6'h1; parameter set2=6'h2; parameter set3=6'h3; parameter set4=6'h4; parameter set5=6'h5; parameter set6=6'h6; parameter dat0=6'h7; parameter dat1=6'h8; parameter dat2=6'h9; parameter dat3=6'hA; parameter dat4=6'hB; parameter dat5=6'hC; parameter dat6=6'hD; parameter dat7=6'hE;

parameter dat8=6'hF; parameter dat9=6'h10; parameter dat10=6'h12; parameter dat11=6'h13; parameter dat12=6'h14; parameter dat13=6'h15; parameter dat14=6'h16; parameter dat15=6'h17; parameter dat16=6'h18; parameter dat17=6'h19; parameter dat18=6'h1A; parameter dat19=6'h1B; parameter dat20=6'h1C; parameter dat21=6'h1D; parameter dat22=6'h1E; parameter dat23=6'h1F; parameter dat24=6'h20; parameter dat25=6'h21; parameter dat26=6'h22; parameter dat27=6'h23; parameter dat28=6'h24; parameter dat29=6'h25; parameter dat30=6'h26; parameter dat31=6'h27; parameter dat32=6'h28; parameter dat33=6'h29; parameter dat34=6'h2A; parameter dat35=6'h2B; parameter dat36=6'h2C; parameter dat37=6'h2E; parameter dat38=6'h2F; parameter dat39=6'h30; parameter dat40=6'h31; parameter dat41=6'h32; parameter dat42=6'h33; parameter dat43=6'h34; parameter nul=6'h35;

always @(posedge clk) begin

counter=counter+1; if(counter==16'h000f) clkr=~clkr; end

always @(posedge clkr)

//da de shi zhong pinlv begin

current=next; case(current)

set0: begin rs<=0; dat<=8'h31; next<=set1; end //*设置8位格式,2行,5*7*

set1: begin rs<=0; dat<=8'h0C; next<=set2; end //*整体显示,关光标,不闪烁*/ set2: begin rs<=0; dat<=8'h6; next<=set3; end //*设定输入方式,增量不移位*/ set3: begin rs<=0; dat<=8'h1; next<=dat0; end //*清除显示*/ dat0: begin rs<=1; dat<=8'hc9; next<=dat1; end //显示第一行 dat1: begin rs<=1; dat<=8'hee; next<=dat2; end dat2: begin rs<=1; dat<=8'hdb; next<=dat3; end dat3: begin rs<=1; dat<=8'hda;next<=dat4; end dat4: begin rs<=1; dat<=8'hca; next<=dat5; end dat5: begin rs<=1; dat<=8'hd0; next<=dat6; end dat6: begin rs<=1; dat<=\ dat7: begin rs<=1; dat<=\ dat8: begin rs<=1; dat<=\ dat9: begin rs<=1; dat<=\ dat10: begin rs<=1; dat<=8'hB5; next<=dat11; end dat11: begin rs<=1; dat<=8'hE7; next<=dat12; end dat12: begin rs<=1; dat<=8'hd7;next<=dat13; end dat13: begin rs<=1; dat<=8'hd3; next<=set4; end

set4: begin rs<=0; dat<=8'h90; next<=dat14; end //显示第二行 dat14: begin rs<=1; dat<=\ dat15: begin rs<=1; dat<=\ dat16: begin rs<=1; dat<=\ dat17: begin rs<=1; dat<=\ dat18: begin rs<=1; dat<=\ dat19: begin rs<=1; dat<=\ dat20: begin rs<=1; dat<=\ dat21: begin rs<=1; dat<=\ dat22: begin rs<=1; dat<=\ dat23: begin rs<=1; dat<=\ dat24: begin rs<=1; dat<=8'hbf; next<=dat25; end dat25: begin rs<=1; dat<=8'haa; next<=dat26; end dat26: begin rs<=1; dat<=8'hb7; next<=dat27; end dat27: begin rs<=1; dat<=8'ha2; next<=dat28; end dat28: begin rs<=1; dat<=8'hb0; next<=dat29; end dat29: begin rs<=1; dat<=8'he5; next<=set5 ; end

set5: begin rs<=0; dat<=8'h88; next<=dat30; end //显示第三行 dat30: begin rs<=1; dat<=\ dat31: begin rs<=1; dat<=\ dat32: begin rs<=1; dat<=\ dat33: begin rs<=1; dat<=\

dat34: begin rs<=1; dat<=8'hbf; next<=dat35; end

dat35: begin rs<=1; dat<=8'hd8; next<=dat36; end dat36: begin rs<=1; dat<=8'hd6; next<=dat37; end dat37: begin rs<=1; dat<=8'hc6; next<=set6; end

set6: begin rs<=0; dat<=8'h9C; next<=dat38; end //显示第四行 dat38: begin rs<=1; dat<=\ dat39: begin rs<=1; dat<=\ dat40: begin rs<=1; dat<=\ dat41: begin rs<=1; dat<=\ end dat42: begin rs<=1; dat<=\ end dat43: begin rs<=1; dat<=\ end

nul: begin rs<=0; dat<=8'h00; if(cnt!=2'h2) begin

e<=0;next<=set0;cnt<=cnt+1; end else

begin next<=nul; e<=1; end end default: next=set0; endcase end

assign en=clkr|e; assign rw=0; endmodule LED花样流水灯 //LED流水灯试验

//利用分频计数器得到显示流水灯的效果 module ledwater (clk_50M,rst,dataout);

input clk_50M,rst; //系统时钟50M输入 从12脚输入。output [11:0] dataout; //我们这里用12个LED灯, reg [11:0] dataout;

reg [27:0] count; //分频计数器 //分频计数器

always @ ( posedge clk_50M ) begin

count<=count+1; end

always @ ( posedge clk_50M or negedge rst) begin

case ( count[27:24] )

// case ( count[25:22] )这一句希望初学者看明白, // 也是分频的关键

// 只有在0的那一位 对应的LED灯才亮。

// 把液晶的E 脚 拉高 0: dataout<=12'b111000111000; 1: dataout<=12'b000111000111; 2: dataout<=12'b110110110110; 3: dataout<=12'b101101101101; 4: dataout<=12'b011011011011; 5: dataout<=12'b000000000000; 6: dataout<=12'b010000010000; 7: dataout<=12'b111000111000; 8: dataout<=12'b111101111101; 9: dataout<=12'b111111111111; 10: dataout<=12'b111101111101; 11:dataout<=12'b111000111000; 12:dataout<=12'b010000010000; 13:dataout<=12'b000000000000; 14:dataout<=12'b111110000011; 15:dataout<=12'b000011111110; endcase end

endmodule PWM+LED

//学习PWM原理,

//拨码开关的 1 2 3 4 5 6 7 8作为输入

//本实验采用拨码开关来控制LED灯的亮暗

//当然如果你的学习板没有拨码开关,可以用key1 key2 key3 key4 作为输入。 //视频教程适合我们21EDA电子的所有学习板 module pwm( switch, clk, led0 );

input clk; //系统时钟输入50M input [7:0]switch; //拨码开关的 1 2 3 4 5 6 7 8作为输入 output led0; //LED灯输出显示亮暗强度 reg led0;

reg [7:0]counter;

always @(posedge clk) begin

counter=counter+1; if(counter>=switch) led0=0; else led0=1; end

endmodule


verilog HDL基础程序(3).doc 将本文的Word文档下载到电脑 下载失败或者文档不完整,请联系客服人员解决!

下一篇:冲孔灌注桩专项施工方案

相关阅读
本类排行
× 注册会员免费下载(下载后可以自由复制和排版)

马上注册会员

注:下载文档有可能“只有目录或者内容不全”等情况,请下载之前注意辨别,如果您已付费且无法下载或内容有问题,请联系我们协助你处理。
微信: QQ: