基于Verilog的FPGA的电子密码锁的设计 - 图文(3)

2019-04-13 22:47

clk1 <= 0;

end end

always@(main_state or correct or error) begin

case(main_state) waits:

if(correct==1) //由waits转换到pass的条件 next_state=pass; else if(error==1&&try_count==1) else

next_state=waits;

next_state=alarm; //由waits转换到alarm的条件

pass:

if(pass_count[7]==1)//由pass转换到waits的条件 next_state=waits;

else next_state=pass; alarm:

if(alarm_count[10]==1)// 由alarm转换到waits的条件 next_state=waits;

else next_state=alarm; default://默认状态:waits next_state=waits;

endcase end

//状态转换

always@(posedge clk1 or negedge resetb) begin

if(!resetb) main_state<=waits; else main_state<=next_state;

end

//输出控制部分

always@(posedge clk1 or negedge resetb)

begin if(!resetb)//复位时,开锁输出与警报输出都为零

begin passed<=8'b00000000;

alarmed<=8'b00000000;

end else if(main_state==pass)//当主机状态为pass时,开锁

begin

passed<=8'b00000001; alarmed<=8'b00000000; end else if(main_state==alarm)//当主机状态为alarm时,警报

begin passed<=8'b00000000;

alarmed<=8'b00000001;

end

else//其它状态复位

begin

passed<=8'b00000000;

alarmed<=8'b00000000; end end

//alarm一段时间后,自动进入waits状态 //alarm定时器

always@(posedge clk1 or negedge resetb) begin

if(!resetb) alarm_count<=0;

else if(main_state==alarm)//alarm状态计时器alarm定时器加1 alarm_count<=alarm_count+1; else alarm_count<=0;

end

//锁pass以后计数开始,当规定的时间到达后自动上锁,并进入waits状态 //pass定时器

always@(posedge clk1 or negedge resetb) begin

if(!resetb) pass_count<=0;

else if(main_state==pass) //pass状态计时器pass定时器加1 pass_count<=pass_count+1; else pass_count<=0;

end

//从状态机,用于输入4位密码

always@(posedge clk1 or negedge resetb) begin if(!resetb)

sub_state<=first; else sub_state<=next_sub_state;

end

always@(!zero||!one||!two||!three||!four||!yes or sub_state) //always@(key or sub_state) begin

if(key_pressed_flag||!yes) if(!yes)//4个密码输完时,进行确认

if

next_sub_state=first;

//default为输入了某位密码,输入完自动将状态转入下一位 else

(!zero||!one||!two||!three||!four)

case(sub_state)

first: next_sub_state=second; second: next_sub_state=third; third: next_sub_state=fourth; fourth:

next_sub_state=finish;

//当输入完4位密码以后状态保持不变,等待输入enter命 //令

finish: next_sub_state=finish; default: next_sub_state=sub_state; endcase

else

next_sub_state=sub_state; end

//比较密码,产生正确或者错误信息 always@(posedge clk1 or negedge resetb) begin

if(!resetb) begin

end

correct<=0; error<=0;

else if(!key_pressed_flag&&!yes) if(password==PASSWORD)//密码正确时

begin correct<=1;

error<=0; end

else//密码错误时

end

begin

error<=1; correct<=0; end else

begin correct<=0; error<=0; end

//记录密码

always@(posedge clk1 or negedge resetb) begin if(!resetb)

password<=0;

else if(!zero||!one||!two||!three||!four)

case(sub_state) first: password[15:12]<=key; second: password[11:8]<=key; third: password[7:4]<=key; fourth: password[3:0]<=key; default: password<=password;

endcase else password<=password;

end

//记录错误次数

always@(posedge clk1 or negedge resetb) begin

if(!resetb) try_count<=0;

else if(error==1)

try_count<=try_count+1;

else if(main_state==pass||main_state==alarm) try_count<=0; end

always@(posedge clk1 or negedge resetb) begin

if(!resetb) begin

key_pressed_flag<=0; key=4'b0000; end

else if(!zero&&change) begin key_pressed_flag<=1;key<=4'b0000; end else if(!one&&change) begin key_pressed_flag<=1;key<=4'b0001; end else if(!two&&change)

begin key_pressed_flag<=1;key<=4'b0010; end else if(!three&&change)

begin key_pressed_flag<=1;key<=4'b0011; end else if(!four&&change)

begin key_pressed_flag<=1;key<=4'b0100; end else if(!zero&&!change) begin key_pressed_flag<=1;key<=4'b0101; end else if(!one&&!change)

begin key_pressed_flag<=1;key<=4'b0110; end else if(!two&&!change)

begin key_pressed_flag<=1;key<=4'b0111; end else if(!three&&!change)

begin key_pressed_flag<=1;key<=4'b1000; end else if(!four&&!change)

begin key_pressed_flag<=1;key<=4'b1001; end else if(!yes)

begin key_pressed_flag<=0;key<=4'b1010; end

End

//diaplay分频后显示 always @(posedge clk0) begin

CNT_R0 <= CNT_R0 + 1'b1;

if(CNT_R0 < 4096) begin

clk0_div <= 1; end else

begin

clk0_div <= 0; end end

////按下change切换输入数的范围


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