88
89output[2:0]M; 90
91wire[2:0]m0,m1,m2; 92
93// Leftmost 2 to 1 Multiplexers 94 95//Top 96
97assign m0[0] = (~S[0]&U[0])|(S[0]&V[0]); 98
99assign m0[1] = (~S[0]&U[1])|(S[0]&V[1]); 100
101assign m0[2] = (~S[0]&U[2])|(S[0]&V[2]); 102
103//Bottom 104
105assign m1[0] = (~S[0]&W[0])|(S[0]&X[0]); 106
107assign m1[1] = (~S[0]&W[1])|(S[0]&X[1]); 108
109assign m1[2] = (~S[0]&W[2])|(S[0]&X[2]); 110
111//Middle Multiplexer 112
113assign m2[0] = (~S[1]&m0[0])|(S[1]&m1[0]); 114
115assign m2[1] = (~S[1]&m0[1])|(S[1]&m1[1]); 116
117assign m2[2] = (~S[1]&m0[2])|(S[1]&m1[2]); 118
119//Last Multiplexer 120
121assign M[0] = (~S[2]&m2[0])|(S[2]&Y[0]); 122
123assign M[1] = (~S[2]&m2[1])|(S[2]&Y[1]); 124
125assign M[2] = (~S[2]&m2[2])|(S[2]&Y[2]); 126
127endmodule 128 129
技巧：同样的选择参数被用于不同的多路选择器实例引用，不同的多路选择器连接不同的数码管，每个数码管都可以循环显示不同的字符。前两部分的代码稍稍修改就可直接引用。
Part VI：用8个数码管循环显示HELLO
要求按照图 3 数码管循环显示，这是整个实验最复杂的部分，需要用到前5部分的信息。因为要用到选择信号的8中状态，需要创建一个8选1的多路选择器。其余就类似第5部分。注意在实例引用8选1多路器时8个输入信号的排列（我的神啊，眼睛差点都看花了J）!!
图3 数码管循环显示 Part VI 代码：
1/* 2
3(C) yf.x 2010 http://halflife.cnblogs.com/ 4
5Filename : part6.v 6
7Compiler : Quartus II 9.1 Web Edition 8
9Description : Demo how to use 8 7seg rotating display 10
11Release : 03/12/2010 1.0 12 13*/ 14
15//Top level file 16
17module part6(SW,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2, 18
19HEX1,HEX0); 20
21input [17:0]SW; 22
23output [0:6]HEX7,HEX6,HEX5,HEX4,HEX3,HEX2, 24HEX1,HEX0; 25
26wire [2:0]M7,M6,M5,M4,M3,M2,M1,M0; 27
28 mux_3bit_8to1 N7(SW[17:15],SW[2:0],SW[2:0],SW[2:0], SW[14:12],SW[11:9],SW[8:6],SW[8:6],SW[5:3],M7); 29
30 mux_3bit_8to1 N6(SW[17:15],SW[2:0],SW[2:0],SW[14:12], SW[11:9],SW[8:6],SW[8:6],SW[5:3],SW[2:0],M6); 31
32 mux_3bit_8to1 N5(SW[17:15],SW[2:0],SW[14:12], 33SW[11:9],SW[8:6],SW[8:6],SW[5:3],SW[2:0],SW[2:0],M5); 34
35 mux_3bit_8to1 N4(SW[17:15],SW[14:12],SW[11:9], 36SW[8:6],SW[8:6],SW[5:3],SW[2:0],SW[2:0],SW[2:0],M4); 37
38 mux_3bit_8to1 N3(SW[17:15],SW[11:9],SW[8:6],SW[8:6], SW[5:3],SW[2:0],SW[2:0],SW[2:0],SW[14:12],M3); 39
40 mux_3bit_8to1 N2(SW[17:15],SW[8:6],SW[8:6],SW[5:3], SW[2:0],SW[2:0],SW[2:0],SW[14:12],SW[11:9],M2); 41
42 mux_3bit_8to1 N1(SW[17:15],SW[8:6],SW[5:3],
43SW[2:0],SW[2:0],SW[2:0],SW[14:12],SW[11:9],SW[8:6],M1); 44
45 mux_3bit_8to1 N0(SW[17:15],SW[5:3],SW[2:0],SW [2:0], SW[2:0],SW[14:12],SW[11:9],SW[8:6],SW[8:6],M0); 46
47 char_7seg H7(M7,HEX7); 48
49 char_7seg H6(M6,HEX6); 50
51 char_7seg H5(M5,HEX5); 52
53 char_7seg H4(M4,HEX4);
54
55 char_7seg H3(M3,HEX3); 56
57 char_7seg H2(M2,HEX2); 58
59 char_7seg H1(M1,HEX1); 60
61 char_7seg H0(M0,HEX0); 62
63endmodule 64
65//3bit 8to1 multiplexer 66
67//use 7 3bit 2-to-1 multiplexer 68
69module mux_3bit_8to1(S,U,V,W,X,Y,Z,A,B,M); 70
71input [2:0]S,U,V,W,X,Y,Z,A,B; 72
73output [2:0]M; 74
75wire [2:0]n0,n1,n2,n3,n4,n5; 76
77// 2 to 1 Multiplexers 78 79//one 80
81assign n0[0] = (~S[0]&U[0])|(S[0]&V[0]); 82
83assign n0[1] = (~S[0]&U[1])|(S[0]&V[1]); 84
85assign n0[2] = (~S[0]&U[2])|(S[0]&V[2]); 86 87//two 88
89assign n1[0] = (~S[0]&W[0])|(S[0]&X[0]); 90
91assign n1[1] = (~S[0]&W[1])|(S[0]&X[1]); 92
93assign n1[2] = (~S[0]&W[2])|(S[0]&X[2]); 94
95//three 96
97assign n2[0] = (~S[0]&Y[0])|(S[0]&Z[0]);
98
99assign n2[1] = (~S[0]&Y[1])|(S[0]&Z[1]); 100
101assign n2[2] = (~S[0]&Y[2])|(S[0]&Z[2]); 102
103//four 104
105assign n3[0] = (~S[0]&A[0])|(S[0]&B[0]); 106
107assign n3[1] = (~S[0]&A[1])|(S[0]&B[1]); 108
109assign n3[2] = (~S[0]&A[2])|(S[0]&B[2]); 110
111//five 112
113assign n4[0] = (~S[1]&n0[0])|(S[1]&n1[0]); 114
115assign n4[1] = (~S[1]&n0[1])|(S[1]&n1[1]); 116
117assign n4[2] = (~S[1]&n0[2])|(S[1]&n1[2]); 118 119//six 120
121assign n5[0] = (~S[1]&n2[0])|(S[1]&n3[0]); 122
123assign n5[1] = (~S[1]&n2[1])|(S[1]&n3[1]); 124
125assign n5[2] = (~S[1]&n2[2])|(S[1]&n3[2]); 126
127//seven 128
129assign M[0] = (~S[2]&n4[0])|(S[2]&n5[0]); 130
131assign M[1] = (~S[2]&n4[1])|(S[2]&n5[1]); 132
133assign M[2] = (~S[2]&n4[2])|(S[2]&n5[2]); 134
135endmodule 136
137//implements a 7_segment decoder for H,E,L,O,and blank 138
139module char_7seg(c,display); 140
141input [2:0]c;