孟磊 简易电子琴的设计 第16页 共21页
END PROCESS;
MUSIC:PROCESS(CLK2) BEGIN
IF(CLK2'EVENT AND CLK2='1')THEN IF(COUNT0 =31)THEN COUNT<=0; ELSE
COUNT<=COUNT0 + 1; END IF; END IF; END PROCESS;
COM1:PROCESS(COUNT,AUTO,INDEX2) BEGIN
IF AUTO='0'THEN CASE COUNT IS
WHEN 0=>INDEX0<=\ WHEN 1=>INDEX0<=\ WHEN 2=>INDEX0<=\ WHEN 3=>INDEX0<=\ WHEN 4=>INDEX0<=\ WHEN 5=>INDEX0<=\ WHEN 6=>INDEX0<=\
WHEN 7=>INDEX0<=\ WHEN 8=>INDEX0<=\ WHEN 9=>INDEX0<=\ WHEN 10=>INDEX0<=\ WHEN 11=>INDEX0<=\ WHEN 12=>INDEX0<=\ WHEN 13=>INDEX0<=\ WHEN 14=>INDEX0<=\
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孟磊 简易电子琴的设计 第17页 共21页
WHEN 15=>INDEX0<=\ WHEN 16=>INDEX0<=\ WHEN 17=>INDEX0<=\ WHEN 18=>INDEX0<=\ WHEN 19=>INDEX0<=\
WHEN 20=>INDEX0<=\ WHEN 21=>INDEX0<=\ WHEN 22=>INDEX0<=\ WHEN 23=>INDEX0<=\ WHEN 24=>INDEX0<=\ WHEN 25=>INDEX0<=\ WHEN 26=>INDEX0<=\ WHEN 27=>INDEX0<=\ WHEN 28=>INDEX0<=\ WHEN 29=>INDEX0<=\ WHEN 30=>INDEX0<=\ WHEN 31=>INDEX0<=\ END CASE;
ELSE INDEX0<=INDEX2; END IF; END PROCESS; END BEHAVIORAL;
2. 音调发生模块的源程序如下所示：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY TONE IS
PORT(INDEX: IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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孟磊 简易电子琴的设计 第18页 共21页
HIGH: OUT STD_LOGIC;
TONE0: OUT INTEGER RANGE 0 TO 2047); END TONE;
ARCHITECTURE ART OF TONE IS BEGIN
SEARCH:PROCESS(INDEX) BEGIN CASE INDEX IS
WHEN\WHEN\WHEN\WHEN\WHEN\WHEN\WHEN\WHEN\WHEN OTHERS=>TONE<=2047;CODE<=\ END CASE; END PROCESS; END ART;
3. 数控分频模块的源程序如下所示：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FENPIN IS
PORT( CLK1: IN STD_LOGIC;
TONE1: IN INTEGER RANGE 0 TO 2047; SPKS: OUT STD_LOGIC); END ENTITY FENPIN;
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孟磊 简易电子琴的设计 第19页 共21页
ARCHITECTURE ART OF FENPIN IS SIGNAL PRECLK:STD_LOGIC; SIGNAL FULLSPKS:STD_LOGIC; BEGIN PROCESS(CLK1)
VARIABLE COUNT:INTEGER RANGE 0 TO 8; BEGIN
IF(CLK'EVENT AND CLK1='1')THEN COUTNT:=COUNT +1; IF COUNT=2 THEN PRECLK<='1'; ELSE COUNT=4 THEN PRECLK<='0';COUTN:=0; END IF; END IF; END PROCESS;
PROCESS(PRECLK,TONE1)
VARIABLE COUNT11:INTEGER RANGE 0 TO 2047; BEGIN
IF(PRECLK'EVENT AND PRECLK='1')THEN IF COUNT11 COUNT11:=COUNT11 +1;FULLSPKS<='1'; ELSE COUNT11:=0;FULLSPKS<='0'; END IF; END IF; END PROCESS; PROCESS(FULLSPKS) VARIABLE COUNT2:STD_LOGIC:='0'; BEGIN 19 孟磊 简易电子琴的设计 第20页 共21页 IF(FULLSPKS'EVENT AND FULLSPKS='1')THEN COUNT2:=NOT COUNT2; IF COUNT2='1'THEN SPKS<='1'; ELSE SPKS<='0'; END IF; END IF; END PROCESS; END PROCESS; END ART; 4. 顶层设计的源代码如下所示： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DIANZIQIN IS PORT(CLK32MHZ: IN STD_LOGIC; HANDTOAUTO: IN STD_LOGIC; CODE1: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); INDEX1: IN STD_LOGIC_VECTOR(7 DOWNTO 0); HIGH1: OUT STD_LOGIC; SPKOUT: OUT STD_LOGIC); END; ARCHITECTURE ART OF DIANZIQIN IS COMPONENT AUTO PORT(CLK: IN STD_LOGIC; AUTO: IN STD_LOGIC; INDEX2:IN STD_LOGIC_VECTOR(7 DOWNTO 0); INDEX0:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 20 孟磊 简易电子琴的设计 第21页 共21页 END COMPONENT; COMPONENT TONE PORT ( INDEX: IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); HIGH: OUT STD_LOGIC; TONE0:OUT INTEGER RANGE 0 TO 2047); END COMPONENT; COMPONENT FENPIN PORT(CLK1: IN STD_LOGIC; TONE1: IN INTEGER RANGE 0 TO 2047; SPKS: OUT STD_LOGIC); END COMPONET; SIGNAL TONE2: INTEGER RANGE 0 TO 2047; SIGNAL INDX: STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN U0:AUTO PORT MAP(CLK=>CLK32MHZ,INDEX2=>INDEX1,INDEX0=>INDX,AUTO=>HANDTOAUTO); U1:TONE PORT MAP(INDEX=>INDX,TONE0=>TONE2,CODE=>CODE1,HIGH=>HIGH1); U2:FENPIN MAP(CLK1=>CLK32MHZ,TONE1=>TONE2,SPKS=>SPKOUT); END ART; PORT 21