initial begin repeat(6) begin
#10 coin=3'b000; #10 coin=3'b001;
#10 coin=3'b010;#10
coin=3'b001;#10
coin=3'b001;#10 coin=3'b001;#10 coin=3'b001;#10
else
case (current) s0:if(a) current<=s1; else current<=s0; s1:if(a) current<=s1; else current<=s2; s2:if(a) current<=s1; else current<=s3; s3:if(a) current<=s4; coin=3'b010;#10 coin=3'b010;#10 coin=3'b010;#10
coin=3'b010;
#10 coin=3'b101;#10
coin=3'b101;#10 coin=3'b101;#10 coin=3'b101;#10
coin=3'b101; end end always #5 clk=~clk; initial #3000 $finish; initial
$monitor($time,\%b,rst=%b\endmodule
2·状态机
利用状态机设计一个“10011”序列检测器，该检测器具有如下行为：在每一个时钟下降沿检查输入数据，当输入数据序列为“10011”时，输出asm被置为1；其余情况asm为0。 要求：画出fsm（有限状态机） 设计代码：
module status_10011(a,clk,rst,asm); input a,clk,rst; output asm;
parameter [2:0] s0 =3'b000, s1 =3'b001, s2 =3'b010, s3 =3'b011, s4 =3'b100, s5 =3'b101; reg [2:0] current; always @ (negedge clk) begin if(rst) current=s0;
else current<=s0; s4:if(a) current<=s5; else current<=s2; s5:if(a) current<=s1; else current<=s2; endcase end
assign asm = (current == s5) ? 1 : 0; endmodule 仿真代码： `timescale 1ns/1ns module status_10011_tb; reg a,clk,rst; wire asm;
status_10011 U1(.a(a),.clk(clk),.rst(rst),.asm(asm)); initial begin
a=0;clk=1;rst=1; end always #5 clk=~clk; always #21 a=~a; initial begin #30 rst=0; #200 rst=1; end initial
$monitor($time,\endmodule