reg one_wire_buf; // One-Wire总线 缓存寄存器
reg [15:0] temperature_buf; //采集到的温度值缓存器（未处理） reg [5:0] step; // 子状态寄存器 0~50 reg [3:0] bit_valid; // 有效位
always @(posedge clk_1us, negedge rst_n) begin
if (!rst_n) begin
one_wire_buf <= 1'bZ; step <= 0; state <= S00;
end else begin
case (state)
S00 : begin
temperature_buf <= 16'h001F;
state <= S0; end
S0 : begin // 初始化 cnt_1us_clear <= 1;
one_wire_buf <= 0; state <= S1; end S1 : begin
cnt_1us_clear <= 0;
if (cnt_1us == 500) // 延时500us begin
cnt_1us_clear <= 1;
one_wire_buf <= 1'bZ; // 释放总线 state <= S2; end
end S2 : begin
cnt_1us_clear <= 0;
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if (cnt_1us == 100) // 等待100us
begin
cnt_1us_clear <= 1; state <= S3; end end
S3 : if (~one_wire) //若18b20拉低总线,初始化成功 state <= S4;
else if (one_wire) // 否则,初始化不成功,返回S0 state <= S0; S4 : begin
cnt_1us_clear <= 0;
if (cnt_1us == 400) // 再延时400us begin
cnt_1us_clear <= 1; state <= S5; end
end
S5 : begin // 写数据 if (step == 0) // 0xCC begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 1) begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 2)
begin one_wire_buf <= 0;
step <= step + 1'b1; state <= WRITE01; end
else if (step == 3) begin
one_wire_buf <= 0;
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step <= step + 1'b1;
state <= WRITE01; end
else if (step == 4) begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 5) begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 6)
begin
one_wire_buf <= 0;
step <= step + 1'b1; state <= WRITE01; end
else if (step == 7)
begin
one_wire_buf <= 0;
step <= step + 1'b1; state <= WRITE01; end
else if (step == 8) // 0x44 begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 9) begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 10) begin
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one_wire_buf <= 0;
step <= step + 1'b1; state <= WRITE01; end
else if (step == 11) begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 12) begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 13) begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 14)
begin
one_wire_buf <= 0;
step <= step + 1'b1; state <= WRITE01; end
else if (step == 15) begin
step <= step + 1'b1; state <= WRITE0;
end
// 第一次写完,750ms后,跳回S0 else if (step == 16) begin
one_wire_buf <= 1'bZ;
step <= step + 1'b1;
state <= S6;
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end
// 再次置数0xCC和0xBE
else if (step == 17) // 0xCC begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 18) begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 19)
begin
one_wire_buf <= 0;
step <= step + 1'b1;
state <= WRITE01; end
else if (step == 20) begin
step <= step + 1'b1; state <= WRITE01; one_wire_buf <= 0; end
else if (step == 21) begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 22) begin
step <= step + 1'b1; state <= WRITE0; end
else if (step == 23) begin
one_wire_buf <= 0;
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