//TASK 2: 将两个模块合成一个 //D/A 5620 运行程序顶层文件： module
top(clk,reset,key,tlc5620_clk,tlc5620_data,tlc5620_load,tlc5620_ldac,sel,ky1,ledcom,leddata); input clk; input reset; input[3:0] key; output tlc5620_clk; output tlc5620_data; output tlc5620_load; output tlc5620_ldac; output[2:0] sel; output ky1; output[7:0] ledcom; output[7:0] leddata; wire a; wire[10:0] b;
tlc5620(.clk(clk),.rst(reset),.write_n(a),.wr_data(b),.dac_clk(tlc5620_clk),.dac_data(tlc5620_data),.dac_load(tlc5620_load),.dac_ldac(tlc5620_ldac));
dac_test(.clk(clk),.rst(reset),.key(key),.wr_n(a),.wr_data(b),.seg_com(ledcom),.seg_data(leddata));
assign ky1=0; assign sel[2]=0; assign sel[1]=0; assign sel[0]=1;
endmodule
////D/A 5620驱动程序： module
tlc5620(clk,rst,write_n,wr_data,dac_clk,dac_data,dac_load,dac_ldac);
parameter CLK_FREQ = 'D50_000_000; //系统时钟50MHZ
parameter DCLK_FREQ = 'D1_000_000; //AD_CLK输出时钟1M/2HZ
always @(posedge clk)
if(DCLK_DIV < (CLK_FREQ / DCLK_FREQ)) DCLK_DIV <= DCLK_DIV+1'b1; else begin
DCLK_DIV <= 0; dac_clk_r <= ~dac_clk_r; end
always @(posedge dac_clk_r or negedge rst) begin if(!rst)
counter <= 0; else
if(counter<='d13)
counter <= counter + 1'b1; else
counter <= 0; end
assign dac_load = (counter == 4'd12) ? 1'b0 : 1'b1; assign dac_clk = (counter > 'd0 && counter < 'd12) ? dac_clk_r : 1'b0;
assign dac_ldac = (counter == 4'd13) ? 1'b0 : 1'b1; assign dac_done = (counter <= 4'd11) ? 1'b0 : 1'b1; assign dac_data = dac_data_r;
/*先高位，把11位数据传输给DAC芯片*/
always @(counter[3:0] or wr_data or dac_done or write_n) begin
if(!dac_done && !write_n) case(counter[3:0])
4'd1: dac_data_r <= wr_data[10]; 4'd2: dac_data_r <= wr_data[9]; 4'd3: dac_data_r <= wr_data[8]; 4'd4: dac_data_r <= wr_data[7]; 4'd5: dac_data_r <= wr_data[6]; 4'd6: dac_data_r <= wr_data[5]; 4'd7: dac_data_r <= wr_data[4]; 4'd8: dac_data_r <= wr_data[3]; 4'd9: dac_data_r <= wr_data[2]; 4'd10: dac_data_r <= wr_data[1]; 4'd11: dac_data_r <= wr_data[0]; default: dac_data_r <= 1'b1; endcase else
dac_data_r <= 1'b1; end
endmodule
/////D/A 5620 测试程序： /* DAC_TLC5620测试模块
* 按KEY1键，通道D的电压值递增; * 按KEY2键，通道C的电压值递增; * 按KEY3键，通道B的电压值递增; * 按KEY4键，通道A的电压值递增; * 各通道的电压值显示于数码管. */ module
dac_test(clk,rst,key,wr_n,wr_data,seg_com,seg_data);
reg [7:0] key3_r; reg [31:0] vo_r;
parameter CLK_FREQ = 'D50_000_000;//系统时钟50MHZ parameter DCLK_FREQ = 'D10;//AD_CLK输出时钟10/2HZ
always @(posedge clk)
if(DCLK_DIV < (CLK_FREQ / DCLK_FREQ)) DCLK_DIV <= DCLK_DIV+1'b1; else begin
DCLK_DIV <= 0; CLK_DIV <= ~CLK_DIV; end
/*高2位为通道选择，低8位为DA数据，第9位 RNG 为1时输出0到2倍Vref，为0时输出0到Vref*/ assign wr_data = {channel,1'b1,data_code_r}; assign wr_n = 1'b0;
/*根据按键不同，选择不同的DA通道，其值递增*/ always @(posedge CLK_DIV or negedge rst ) if(!rst) begin
key0_r <= 8'h00; key1_r <= 8'h00; key2_r <= 8'h00; key3_r <= 8'h00; data_code_r <= 8'h00;
end else case(key)
4'b1110 : begin //key4 channel <= 2'b00; key0_r <= key0_r + 1'b1; data_code_r <= key0_r; end 4'b1101 : begin //key3 channel <= 2'b01; key1_r <= key1_r + 1'b1; data_code_r <= key1_r; end 4'b1011 : begin //key2 channel <= 2'b10; key2_r <= key2_r + 1'b1; data_code_r <= key2_r; end 4'b0111 : begin //key1 channel <= 2'b11; key3_r <= key3_r + 1'b1; data_code_r <= key3_r; end default : begin end endcase
/*将各通道的电压值显示于数码管上，单位mv */ always @(negedge rst or negedge CLK_DIV ) begin if(!rst) begin datain[0]<=8'b00000000; datain[1]<=8'b00000000; datain[2]<=8'b00000000; datain[3]<=8'b00000000; datain[4]<=8'b00000000; datain[5]<=8'b00000000; datain[6]<=8'b00000000; datain[7]<=8'b00000000;
end
else begin
/*电压值Vo=Vref * (RNG+1) * CODE / 256 */
vo_r = data_code_r * 13'd5000/9'd256;
datain[0]<=vo_r; /*% 表示取模*/
datain[1]<=vo_r/10; datain[2]<=vo_r/100;
datain[3]<=vo_r/1000;
end
end
always @(posedge clk) begin count=count+1;
end
always @(count[14:12]) begin case(count[14:12]) 3'b000: begin
bcd_led = datain[0]; //数码管扫描 seg_com = 8'b00000001; //数码管共阳极 end 3'b001: begin
bcd_led=datain[1]; seg_com=8'b00000010; end 3'b010: begin
bcd_led=datain[2]; seg_com=8'b00000100; end 3'b011: begin
bcd_led=datain[3]; seg_com=8'b00001000; end 3'b100: begin
bcd_led=datain[4]; seg_com=8'b00010000; end 3'b101: begin
bcd_led=datain[5]; seg_com=8'b00100000; end 3'b110: begin
bcd_led=datain[6]; seg_com=8'b01000000; end 3'b111: begin
bcd_led=datain[7]; seg_com=8'b10000000;
end
endcase
end
always @(seg_com or bcd_led) begin case(bcd_led[3:0]) 4'h0:seg_data=8'hc0; //11000000 显示 0 4'h1:seg_data=8'hf9; //11111001 显示 1 4'h2:seg_data=8'ha4; //..... 4'h3:seg_data=8'hb0; //..... 4'h4:seg_data=8'h99; //..... 4'h5:seg_data=8'h92; 4'h6:seg_data=8'h82; 4'h7:seg_data=8'hf8; 4'h8:seg_data=8'h80; 4'h9:seg_data=8'h90; 4'ha:seg_data=8'h88; 4'hb:seg_data=8'h83; 4'hc:seg_data=8'hc6; 4'hd:seg_data=8'ha1; 4'he:seg_data=8'h86;
4'hf:seg_data=8'h8e;
endcase
end
endmodule