基于单片机步进电机控制器的设计
pulled low will source current (IIL) because of the internal pullups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data mem?ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features of the AT89C51 as listed below:
Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe)
Port 3 also receives some control signals for Flash pro?gramming and verification. RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.
In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external tim?ing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only dur?ing a MOVX or MOVC instruction. Otherwise, the pin is
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安徽工程大学毕业设计（论文）
weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external pro-gram memory.
When the AT89C51 is executing code from external pro-gram memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external pro-gram memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable volt-age (VPP) during Flash programming, for parts that require 12-volt VPP.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2
Output from the inverting oscillator amplifier. Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maxi-mum voltage high and low time specifications must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the spe?cial functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execu?tion, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
Power-down Mode
In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Regis ters retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level
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基于单片机步进电机控制器的设计
and must be held active long enough to allow the oscillator to restart and stabilize.
Program Memory Lock Bits
On the chip are three lock bits which can be left unpro?grammed (U) or can be programmed (P) to obtain the additional features listed in the table below.
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow?ered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is nec?essary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.
Programming the Flash
The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage program?ming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third-party Flash or EPROM programmers.
The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.
VPP = 12V VPP = 5V
Top-Side Mark AT89C51 AT89C51 xxxx yyww xxxx-5 yyww
Signature (030H) = 1 EH (030H) = 1 EH
(031H) = 51H (031H) = 51H (032H) =F FH (032H) = 05H
The AT89C51 code memory array is programmed byte-by?byte in either programming mode. To program any non-blank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.
Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1.Input the desired memory location on the address lines.2.Input the appropriate data byte on the data lines.3.Activate the correct combination of control signals.4.Raise EA/VPP to 1 2V for the high-voltage program?ming mode.5.Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the addressand data for the entire array or until the end of the object file is reached.
Data Polling: The AT89C51 features Data Polling to indi?cate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the com?plement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on
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安徽工程大学毕业设计（论文）
all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.
Chip Erase: The entire Flash array is erased electrically by using theproper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all ―1‖s. The chip erase operation must be executed before the code memory can be re-programmed.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031 H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.
(030H) = 1 EH indicates manufactured by Atmel (031 H) = 51 H indicates 89C51
(032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming Programming Interface .Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combi?nation of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion.All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.
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基于单片机步进电机控制器的设计
AT89C51 单片机性能研究
AT89C51是美国ATMEL 公司生产的低电压，高性能8位单片机，片内含4k字节的可反复擦写的只读程序存储器和128字节的随机存取数据存储器（RAM ) ，器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS一51指令系统，片内置通用8 位中央处理器（CPU）和Flash 存储单元，功能强大AT89C51 单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
主要性能参数：与MCS—51产品指令系统完全兼容；4k字节可重擦写Flash 闪速存储器；1000 次擦写周期；全静态操作：0Hz—24MHZ；三级加密程序存储器；128x8 字节内部RAM；32 个可编程I/O 口线；2 个16 位定时/计数器；6 个中断源；可编程串行UART 通道；低功耗空闲和掉电模式。
功能特性概述：
VCC:电源电压。 GND:地。
AT89C51 提供以下标准功能：4k字节Flash闪速存储器，128字节内部RAM，32个I/O 口线，两个16 位定时/计数器，一个5 向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU 的工作，但允许RAM ，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM 中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。
引脚说明 :
?P0 口：PO 口是一组8 位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能吸收电流的方式驱动8 个TTL 逻辑门电路，对端口写―1‖ 可作为高阻抗输入端用。
在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。
在Flash 编程时，PO 口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。
?Pl口：Pl 是一个带内部上拉电阻的8 位双向I/O口，Pl 的输出缓冲级可驱动（吸收或输出电流）4 个TTL 逻辑门电路。对端口写―1 \，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。
Flash 编程和程序校验期间，Pl 接收低8 位地址。
?P2口：P2 是一个带有内部上拉电阻的8 位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL 逻辑门电路。对端口写―1 \，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IlL ）。
在访问外部程序存储器或16 位地址的外部数据存储器（例如执行MOVX @ DPTR 指令）时，P2 口送出高8 位地址数据。在访问8 位地址的外部数据存储器（如执行MOVX @RI指令）时，P2 口线上的内容（也即特殊功能寄存器（SFR ) 区中R2 寄存器的内容），在整个访问期间不改变。
Flash 编程或校验时，PZ 亦接收高位地址和其它控制信号。
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