如何使用Debussy与ModelSim做Co-Simulation (SOC) (Verilog) (VH(4)

RTL部分 (以4 bit counter為例) counter.vhd / VHDL

1 -- (C) OOMusou 2011 http://oomusou.cnblogs.com 2

3 -- Filename : counter.vhd

4 -- Simulator : ModelSim 6.3e, Debussy 5.4 v9 5 -- Description : ModelSim with debussy 6 -- Release : 02/05/2011 1.0 7

8 library IEEE;

9 use IEEE.std_logic_1164.all; 10 use IEEE.std_logic_unsigned.all; 11

12 entity counter is

13 port ( clk : in std_logic; 14 rst_n : in std_logic;

15 cnt : out std_logic_vector(3 downto 0)); 16 end entity counter; 17

18 architecture arc of counter is

19 signal cnt_r : std_logic_vector(3 downto 0); 20 begin

21 process(clk, rst_n) 22 begin

23 if (rst_n = '0') then 24 cnt_r <= \;

25 elsif rising_edge(clk) then 26 cnt_r <= cnt_r + 1; 27 end if; 28 end process; 29

30 cnt <= cnt_r; 31 end arc; 复制代码

Step 3： Testbench部分

counter_tb.v / Verilog

1 /*

2 (C) OOMusou 2011 http://oomusou.cnblogs.com 3

4 Filename : counter_tb.v

5 Compiler : ModelSim 6.3e, Debussy 5.4 v9 6 Description : ModelSim with debussy 7 Release : 01/31/2010 1.0 8 */ 9

10 module counter_tb; 11

12 reg clk; 13 reg rst_n; 14 wire [3:0] cnt; 15

16 // 50MHz

17 always #(10) clk = ~clk; 18

19 initial begin 20 #0;

21 clk = 1'b0; 22 rst_n = 1'b0; 23 24 #5;

25 rst_n = 1'b1; 26 #195; 27 $finish; 28 end 29

30 initial begin

31 $fsdbDumpfile(\); 32 $fsdbDumpvars(1, counter_tb); 33 end 34

35 counter u_counter ( 36 .clk(clk), 37 .rst_n(rst_n), 38 .cnt(cnt) 39 ); 40

41 endmodule 复制代码

30行

initial begin

$fsdbDumpfile(\);

$fsdbDumpvars(1, counter_tb); end 复制代码

$fsdbDumpvars()的第一個參數是填1不是0，若填0會產生以下warning，不過並不影響最後fsdb的結果。

# ** Warning: Unknown scope type: counter_tb.u_counter 1010 # : counter_tb.v(30)

# Time: 0 ns Iteration: 0 Instance: /counter_tb

# ** Warning: Unknown scope type: counter_tb.u_counter 1010 # : counter_tb.v(30)

# Time: 0 ns Iteration: 0 Instance: /counter_tb # *Novas* End of dumping. 复制代码

Step 4：

ModelSim script部分 vsim.do

vlib work

vcom counter.vhd vlog counter_tb.v vsim counter_tb run 200ns q 复制代码

VHDL使用vcom編譯，Verilog使用vlog編譯。 Step 5：

執行ModelSim的批次檔 mod.bat

vsim -c -do sim.do

執行結果

D:\\0Clare\\VerilogLab\\ModelSim\\counter_vhdl_verilog>vsim -c -do sim.do Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl # 6.3e

# do sim.do

# ** Warning: (vlib-34) Library already exists at \

# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter

# -- Compiling architecture arc of counter

# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008 # -- Compiling module counter_tb #

# Top level modules: # counter_tb # vsim counter_tb

# Loading C:\\Modeltech_6.3e\\win32/novas.dll # // ModelSim SE 6.3e Feb 2 2008 # //

# // Copyright 1991-2008 Mentor Graphics Corporation # // All Rights Reserved. # //

# // THIS WORK CONTAINS TRADE SECRET AND

# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS # // AND IS SUBJECT TO LICENSE TERMS. # //

# Loading work.counter_tb(fast) # Loading std.standard

# Loading ieee.std_logic_1164(body) # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_unsigned(body) # Loading work.counter(arc)

# Novas FSDB Dumper for ModelSim, Release 5.4v9 (Win95/NT) 05/04/2005 # Copyright (C) 1996 - 2004 by Novas Software, Inc. # *Novas* Create FSDB file 'counter.fsdb'

# *Novas* Start dumping the scope(counter_tb), layer(0). # ** Warning: Unknown scope type: counter_tb.u_counter 1010 # : counter_tb.v(30)

# Time: 0 ns Iteration: 0 Instance: /counter_tb

# ** Warning: Unknown scope type: counter_tb.u_counter 1010 # : counter_tb.v(30)

# Time: 0 ns Iteration: 0 Instance: /counter_tb # *Novas* End of dumping.

D:\\0Clare\\VerilogLab\\ModelSim\\counter_vhdl_verilog>vsim -c -do sim.do

Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl # 6.3e

# do sim.do

# ** Warning: (vlib-34) Library already exists at \

# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter

# -- Compiling architecture arc of counter

# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008 # -- Compiling module counter_tb #

# Top level modules: # counter_tb # vsim counter_tb

# ** Note: (vsim-3813) Design is being optimized due to module recompilation... # ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.

# Loading C:\\Modeltech_6.3e\\win32/novas.dll # // ModelSim SE 6.3e Feb 2 2008 # //

# // Copyright 1991-2008 Mentor Graphics Corporation # // All Rights Reserved. # //

# // THIS WORK CONTAINS TRADE SECRET AND

# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS # // AND IS SUBJECT TO LICENSE TERMS. # //

# Loading work.counter_tb(fast) # Loading std.standard

# Loading ieee.std_logic_1164(body) # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_unsigned(body) # Loading work.counter(arc)

# Novas FSDB Dumper for ModelSim, Release 5.4v9 (Win95/NT) 05/04/2005 # Copyright (C) 1996 - 2004 by Novas Software, Inc. # *Novas* Create FSDB file 'counter.fsdb'

# *Novas* Start dumping the scope(counter_tb), layer(1). # *Novas* End of dumping.