end ycounter;
architecture a_ycounter of ycounter is begin
PROCESS (clk)
VARIABLE cnt :std_logic_vector(7 downto 0); BEGIN
IF (clk'EVENT AND clk = '1') THEN IF(clear = '0') THEN cnt := \ ELSE
IF(ld = '0') THEN cnt := d; ELSE
IF(enable = '1') THEN cnt := cnt + \ END IF; END IF; END IF; END IF; qk <= cnt; END PROCESS; end a_ycounter; 测试向量如下：
-- VHDL Test Bench Created from source file ycounter.vhd -- 16:50:55 03/24/2008 -- Notes:
-- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. --
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL;
ENTITY ycounter_a_ycounter_vhd_tb IS END ycounter_a_ycounter_vhd_tb;
ARCHITECTURE behavior OF ycounter_a_ycounter_vhd_tb IS
COMPONENT ycounter PORT(
clk : IN std_logic; clear : IN std_logic; ld : IN std_logic; enable : IN std_logic;
d : IN std_logic_vector(7 downto 0); qk : OUT std_logic_vector(7 downto 0) );
END COMPONENT;
constant clk_cycle: time:=20 us; SIGNAL clk : std_logic; SIGNAL clear : std_logic; SIGNAL ld : std_logic; SIGNAL enable : std_logic;
SIGNAL d : std_logic_vector(7 downto 0); SIGNAL qk : std_logic_vector(7 downto 0);
BEGIN
uut: ycounter PORT MAP(
clk => clk, clear => clear, ld => ld, enable => enable, d => d,
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);
qk => qk
-- *** Test Bench - User Defined Section *** u1 : PROCESS BEGIN clk<='0'; wait for clk_cycle/2; clk<='1';
wait for clk_cycle/2; clk<='0';
wait for clk_cycle/2; clk<='1';
wait for clk_cycle/2; clk<='0';
wait for clk_cycle/2; clk<='1';
wait for clk_cycle/2; clk<='0';
wait for clk_cycle/2; clk<='1';
wait for clk_cycle/2; clk<='0';
wait for clk_cycle/2; clk<='1';
wait for clk_cycle/2; clk<='0';
wait for clk_cycle/2; clk<='1';
wait for clk_cycle/2; clk<='0';
wait for clk_cycle/2;
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clk<='1';
wait for clk_cycle/2; clk<='0';
wait for clk_cycle/2; clk<='1';
wait ;
END PROCESS u1; u2: process begin clear<='0'; wait for clk_cycle;
clear<='1';
wait;
end process;
u3: process begin ld<='1';
wait for clk_cycle*6;
ld<='0';
wait ;
end process u3;
u4: process begin enable<='1'; wait ;
end process u4;
u5: process begin d<=\ wait;
end process u5;
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-- *** End Test Bench - User Defined Section *** END behavior; 仿真图图下：
六、预习与思考：
思考：VHDL语言中信号和变量有什么区别？
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