（三）数据选择模块
1、VHDL源程序 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity sjxz is
port (a,b,c: in std_logic_vector(3 downto 0);
clk2,rst: in std_logic;
s: out std_logic_vector(1 downto 0); y: out std_logic_vector(3 downto 0) ); end sjxz;
architecture body_chooser of sjxz is
signal count: std_logic_vector (1 downto 0); begin
s<=count; process(clk2,rst) begin
if(rst='0')then count<=\ elsif(clk2'event and clk2='1')then if(count>=\
count<=\ else count<=count+1; end if;
end if; case count is when \ when \ when \
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when others=>null; end case; end PROCESS; end body_chooser; 2、仿真图
（四）报警模块
1、VHDL源程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ALARM IS
PORT(CLK,I:IN STD_LOGIC; Q:OUT STD_LOGIC); END ALARM;
ARCHITECTURE BEHAVE OF ALARM IS BEGIN
PROCESS(I,CLK) BEGIN
IF I='0' THEN q <='0'; ELSIF I='1' THEN q<=clk; END IF;
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END PROCESS; END BEHAVE; 2、仿真图
（五）译码模块 1、VHDL源程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY YMQ IS
PORT(AIN4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END YMQ;
ARCHITECTURE ART OF YMQ IS BEGIN
PROCESS(AIN4) BEGIN CASE AIN4 IS
WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \
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WHEN \ WHEN \ WHEN OTHERS=>DOUT7<=\ END CASE; END PROCESS; END ARCHITECTURE ART; 2、仿真图
（六）控制模块
1、VHDL源程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY kongzhi IS PORT( c,p:in std_logic;
);
o :out std_logic
end kongzhi;
architecture s_1 of kongzhi is begin
process(p,c)
begin
if p='1' then o<='0';
elsif p='0' then o<=c;
end if; end process; end s_1;
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2、仿真图
（七）主电路连线图
（八）将程序下载到芯片FLEX—EPF10LC84-4上，引脚图如下
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